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The ZipCPU by Gisselquist Technology

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The ZipCPU by Gisselquist Technology

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The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

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Cabeçalhos

H1	H2	H3	H4	H5	H6
1	270	0	0	0	0

[H1] Blog Posts
[H2] Device Clock Generation
[H2] Quiz #24: Is there an AXI bug here?
[H2] Comparing the Xilinx MIG with an open source DDR3 controller
[H2] Wrap addressing
[H2] Your problem is not AXI
[H2] My Personal Journey in Verification
[H2] Debugging video from across the ocean
[H2] Bringing up Kimos
[H2] Chasing resets
[H2] 2023, Year in review
[H2] An Overview of a 10Gb Ethernet Switch
[H2] SDIO RX: Bugs found w/ Formal methods
[H2] Using a Verilog task to simulate a packet generator for an SDIO controller
[H2] Introducing the ZipCPU v3.0
[H2] What is a Virtual Packet FIFO?
[H2] What is a SwiC?
[H2] Debugging the Hard Stuff
[H2] Your soft-core CPU won't boot. Where should you start debugging?
[H2] Thanksgiving! I have much to be thankful for
[H2] Quiz #23: Can this assertion fail?
[H2] A first lesson in sales pitches: Honesty
[H2] Quiz #22: Handling cover failures
[H2] Measuring the Steps to Design Checkoff
[H2] Assignment delay's and Verilog's wait statement
[H2] It's not my fault! Your code is broken.
[H2] Protocol Design for Network Debugging
[H2] Quiz #21: Verifying all configurations of a design
[H2] ZipCPU Lesson: If it's not tested, it doesn't work.
[H2] A Coming Economic Downturn? or Worse?
[H2] Quiz #20: Using $stable in a multiclock environment
[H2] Learning AXI: Where to start?
[H2] Bringing up a new piece of hardware -- what can go wrong?
[H2] Rethinking Video with AXI video streams
[H2] AXI Stream is broken
[H2] 2020 and 2021 in review
[H2] Quiz #19: Using disable iff in a concurrent assertion
[H2] Creating a Simple AXI-Lite Master for the Hexbus
[H2] Envisioning the Ultimate I2C Controller
[H2] Clock Gating
[H2] Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
[H2] Quiz #18: Failures in clocked immediate assertions
[H2] AXI Handshaking Rules
[H2] Measuring AXI latency and throughput performance
[H2] Quiz #17: Induction failures
[H2] The other half of the Gospel
[H2] CPU based simulation, first thoughts
[H2] Quiz #16: Immediate assertions in the presence of asynchronous resets
[H2] Building a Better Verilog Multiply for the ZipCPU
[H2] Examples of AXI4 bus masters
[H2] Quiz #15: Pass-through memory
[H2] Fixing Xilinx's Broken AXI-lite Design in VHDL
[H2] Building a Simple AXI-lite Memory Controller
[H2] Common AXI Themes on Xilinx's Forum
[H2] Whatever happened to the ZipOS?
[H2] Lessons learned while building an ASIC design
[H2] The FPGA designer who didn't get the job
[H2] Ultimate Logic
[H2] Quiz #14: Two nearly identical frequencies
[H2] Formally verifying register handling
[H2] Is it possible to make a living as a solo digital design engineer?
[H2] Spectrograms need Window Functions
[H2] A fun Friday evening--verifying an AXI-lite slave
[H2] Moving values and strobes cross clock domains
[H2] Quiz #13: Temporal assertion equivalences
[H2] Run length encoding an AXI stream
[H2] Driving an output on both edges of the clock
[H2] Building a Downsampling Filter
[H2] I have a brand new piece of IP. How shall I verify it?
[H2] Measuring clock speed
[H2] The hard part of building a bursting AXI Master
[H2] Four keys to getting your design to work the first time
[H2] Quiz #12: Catching extraneous acknowledgments
[H2] Building a Protocol Firewall
[H2] Debugging AXI Streams
[H2] Adding an AXI-Lite interface to your Verilator test script
[H2] Re: What does your design flow look like?
[H2] Building a basic AXI Master
[H2] Cheap Spectral Estimation
[H2] Locally resetting an AXI component
[H2] Adjusting our logic PLL to handle I&Q
[H2] Buidilng an AXI-Lite slave the easy way
[H2] The Faith of a Mustard Seed
[H2] A Histogram Gone Bad
[H2] Quiz #11: Induction and clock enables
[H2] Quiz #10: Checking stall conditions
[H2] Lessons in Hardware Reuse
[H2] 2019: AXI Meets Formal Verification
[H2] The Christmas Gospel
[H2] Using a Histogram to Debug A/D Data Streams
[H2] Quiz #9: Immediate assertions midst blocking assignments
[H2] Quiz #8: Will this pass a bounded model check?
[H2] The ZipCPU meets blinky
[H2] Formally Verifying a General Purpose Ultra-Micro Controller
[H2] Quiz #7: Returning to $past() and our counter again
[H2] Putting the pieces together to build a data recorder
[H2] Is formal verfication enough, or is simulation required?
[H2] Quiz #6: Synchronous logic in Asynchronous contexts
[H2] AXI Verification, the story so far
[H2] Understanding AutoFPGA's address assignment algorithm
[H2] Quiz #5: Immediate vs Concurrent Assertions
[H2] Connecting lots of slaves to a bus without using a lot of logic
[H2] Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
[H2] Technology Debt and AutoFPGA, the bill just came due
[H2] Xilinx deleted this post
[H2] Quiz #3: Will formal verification prove this counter keeps its bounds?
[H2] Planning an Intermediate Design Tutorial
[H2] Quiz #2: Will this counter pass formal verification?
[H2] Quiz #1: Will the assertion below ever fail?
[H2] Just how long does a formal proof take to finish?
[H2] Lessons learned while building crossbar interconnects
[H2] Breaking all the rules to create an arbitrary clock signal
[H2] Building the perfect AXI4 slave
[H2] Building a Skid Buffer for AXI processing
[H2] Examining Xilinx's AXI demonstration core
[H2] Understanding AXI Addressing
[H2] Project Ideas: PMod AMP2
[H2] Applying Formal Methods to the Events of the Resurrection
[H2] The most common AXI mistake
[H2] The ZipCPU's Interrupt Controller
[H2] Logic usage and decoding return results with cascaded multiplexers
[H2] Building a universal QSPI flash controller
[H2] Introducing the ArrowZip ZipCPU design, featuring the Max-1000
[H2] Using Sequence Properties to Verify a Serial Port Transmitter
[H2] Why does blinky make a CPU appear to be so slow?
[H2] Debugging a CPU
[H2] Building a custom yet functional AXI-lite slave
[H2] ZipCPU highlights from 2018
[H2] Using a formal property file to verify an AXI-lite peripheral
[H2] AutoFPGA's linker script support gets an update
[H2] Makefiles for formal proofs with SymbiYosys
[H2] Swapping assumptions and assertions doesn't work
[H2] Building a video controller: it's just a pair of counters
[H2] Accessing the registers of a SoC+FPGA
[H2] Taking a look at the TinyFPGA BX
[H2] To my new readers and my new twitter followers, welcome!
[H2] An Open Source Pipelined FFT Generator
[H2] It's time for ORCONF 2018!
[H2] My design works in simulation, but not in hardware. Can formal methods help me?
[H2] Handling multiple clocks with Verilator
[H2] RE: Building a simulation for my design? What does that mean?
[H2] How to build a SPI Flash Controller for an FPGA
[H2] Reasons why Synthesis might not match Simulation
[H2] Why I like Formal: the ZipCPU and the ICO board
[H2] What does Formal Development look like in Practice?
[H2] Formally Verifying Memory and Cache Components
[H2] Crossing clock domains with an Asynchronous FIFO
[H2] Formally Verifying Asynchronous Components
[H2] A Slow but Symmetric FIR Filter Implementation
[H2] Updated Projects List
[H2] Aggregating verified modules together
[H2] ZipTimer: A simple countdown timer
[H2] Formally Verifying an Asynchronous Reset
[H2] What would you like to see on the ZipCPU blog?
[H2] Will formal methods ever find a bug in a working CPU?
[H2] Resurrection Day!
[H2] Quadratic fits are entirely inappropriate for DSP
[H2] Pipelining a Prefetch
[H2] Is formal really all that hard?
[H2] An Exercise in using Formal Induction
[H2] Want to use ZBasic? Let's have some fun--no actual FPGA required!
[H2] Debugging a Cyclone-V
[H2] ZipCPU toolchain and initial test
[H2] Updating ZipCPU files
[H2] Interpolation is just a special type of convolution
[H2] A Quick Introduction to the ZipCPU Instruction Set
[H2] Top 10 ZipCPU blog posts for 2017
[H2] A better filter implementation for slower signals
[H2] Mystery post: The ugliest bug I've ever encountered
[H2] Arrow's Max-1000: A gem for all the wrong reasons
[H2] Building a Simple Logic PLL
[H2] Building a Numerically Controlled Oscillator
[H2] Testing the fast, generic FIR filter
[H2] Thank you!
[H2] Measuring the frequency response of a filter under test
[H2] Building a prefetch module for the ZipCPU
[H2] Generating more than one bit at a time with an LFSR
[H2] An example LFSR
[H2] A Configurable Signal Delay Element
[H2] Building Formal Assumptions to Describe Wishbone Behaviour
[H2] The Interface to a Generic Filtering Testbench
[H2] Good Software Engineering Principles Apply to Students Too
[H2] Generating Pseudo-Random Numbers on an FPGA
[H2] Some Simple Clock-Domain Crossing Solutions
[H2] My first experience with Formal Methods
[H2] Just some notes to new readers of the ZipCPU blog
[H2] Implementing the Moving Average (Boxcar) filter
[H2] FPGAs vs ASICs
[H2] It's all about the interfaces
[H2] Using AutoFPGA to connect simple registers to a debugging bus
[H2] A Brief Introduction to AutoFPGA
[H2] A CORDIC testbench
[H2] A Cheaper Fast FIR Filter
[H2] Understanding the effects of Quantization
[H2] Clocks for Software Engineers
[H2] Demonstrating the improved PWM waveform
[H2] Building a high speed Finite Impulse Response (FIR) Digital Filter
[H2] Even I get stuck in FPGA Hell
[H2] Glad I went to ORCONF
[H2] Off to ORCONF-2017!
[H2] Reinventing PWM
[H2] Big Money Engineering Integrity
[H2] CORDIC part two: rectangular to polar conversion
[H2] Using a CORDIC to calculate sines and cosines in an FPGA
[H2] Building a quarter sine-wave lookup table
[H2] Debugging your soft-core CPU within an FPGA
[H2] The ZipCPU's pipeline logic
[H2] Rules for new FPGA designers
[H2] Two of the Simplest Digital filters
[H2] Strategies for pipelining logic
[H2] What would cause you to lie?
[H2] A Simple ALU, drawn from the ZipCPU
[H2] Series: Debouncing in Digital Logic
[H2] Using a debug-bus to Measure Bouncing
[H2] Measuring Contact Bounce
[H2] How to eliminate button bounces with digital logic
[H2] Visualizing Contact Bounce
[H2] ZipCPU Advertising
[H2] Writing your own VCD File
[H2] Linear Interpolation
[H2] Getting the basic FIFO right
[H2] Windows FPGA designers may not need a Linux machine ... yet
[H2] How to build a simulation based debugger for your own soft-core CPU
[H2] How to Debug a DSP algorithm
[H2] Rounding Numbers without Adding a Bias
[H2] Bit growth in FPGA arithmetic
[H2] A Basic Upsampling Linear Interpolator
[H2] Verilator doesn't find everything (today)
[H2] Design Needs when Debugging a SoftCore CPU
[H2] The simplest sine wave generator within an FPGA
[H2] Getting Started with the Wishbone Scope
[H2] Finishing off the debugging bus: building a software interface
[H2] Why you want a debug port into your FPGA
[H2] Simulating an FPGA through the debugging interface
[H2] My own FPGA debugging philosophy
[H2] Building a very simple wishbone interconnect
[H2] Taking a New Look at Verilator
[H2] Putting our Debugging Bus RTL Components Together
[H2] Sending bus idle notifications down the line
[H2] Why Use a Network Interface to your FPGA
[H2] Support me on Patreon
[H2] The debugging bus: a goal for FPGA interaction
[H2] Adding interrupt reporting to our debugging bus
[H2] How to send our bus results back out the serial port
[H2] No PI for you
[H2] How to create bus command words, from a 7-bit data stream
[H2] Minimizing FPGA Resource Utilization
[H2] A College Student's Response to the FPGA Design Process
[H2] Building a Simple Wishbone Master
[H2] Building A Simple In-Circuit Logic Analyzer
[H2] Nearest Neighbor Interpolation
[H2] An Overview of a Wishbone-UART Bridge
[H2] Campus Sidewalks and FPGA Design
[H2] Controlling Timing within an FPGA
[H2] The Actual FPGA Design Process
[H2] Building a simple wishbone slave
[H2] Bus Select Lines
[H2] FFT debugging
[H2] Debugging an FPGA through the serial port--first steps
[H2] That first serial port: Debugging when you are blind
[H2] Building a simple bus
[H2] Moving to memory
[H2] A Vision for Controlling FPGA Logic
[H2] Which comes first: the CPU or the peripherals?
[H2] Knight Rider
[H2] FPGA Hell
[H2] Blinky
[H2] Most common Digilent FPGA support requests
[H2] Cannot be done
[H2] Welcome to the ZipCPU blog!
[H2] The ZipCPU by Gisselquist Technology

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Âncoras	Tipo	Sumo
About Us	Internas	Passa sumo
FPGA Hell	Internas	Passa sumo
Tutorial	Internas	Passa sumo
Formal training	Internas	Passa sumo
Quizzes	Internas	Passa sumo
Projects	Internas	Passa sumo
Site Index	Internas	Passa sumo
Device Clock Generation	Internas	Passa sumo
Quiz #24: Is there an AXI bug here?	Internas	Passa sumo
Comparing the Xilinx MIG with an open source DDR3 controller	Internas	Passa sumo
Wrap addressing	Internas	Passa sumo
Your problem is not AXI	Internas	Passa sumo
My Personal Journey in Verification	Internas	Passa sumo
Debugging video from across the ocean	Internas	Passa sumo
Bringing up Kimos	Internas	Passa sumo
Chasing resets	Internas	Passa sumo
2023, Year in review	Internas	Passa sumo
An Overview of a 10Gb Ethernet Switch	Internas	Passa sumo
SDIO RX: Bugs found w/ Formal methods	Internas	Passa sumo
Using a Verilog task to simulate a packet generator for an SDIO controller	Internas	Passa sumo
Introducing the ZipCPU v3.0	Internas	Passa sumo
What is a Virtual Packet FIFO?	Internas	Passa sumo
What is a SwiC?	Internas	Passa sumo
Debugging the Hard Stuff	Internas	Passa sumo
Your soft-core CPU won't boot. Where should you start debugging?	Internas	Passa sumo
Thanksgiving! I have much to be thankful for	Internas	Passa sumo
Quiz #23: Can this assertion fail?	Internas	Passa sumo
A first lesson in sales pitches: Honesty	Internas	Passa sumo
Quiz #22: Handling cover failures	Internas	Passa sumo
Measuring the Steps to Design Checkoff	Internas	Passa sumo
Assignment delay's and Verilog's wait statement	Internas	Passa sumo
It's not my fault! Your code is broken.	Internas	Passa sumo
Protocol Design for Network Debugging	Internas	Passa sumo
Quiz #21: Verifying all configurations of a design	Internas	Passa sumo
ZipCPU Lesson: If it's not tested, it doesn't work.	Internas	Passa sumo
A Coming Economic Downturn? or Worse?	Internas	Passa sumo
Quiz #20: Using $stable in a multiclock environment	Internas	Passa sumo
Learning AXI: Where to start?	Internas	Passa sumo
Bringing up a new piece of hardware -- what can go wrong?	Internas	Passa sumo
Rethinking Video with AXI video streams	Internas	Passa sumo
AXI Stream is broken	Internas	Passa sumo
2020 and 2021 in review	Internas	Passa sumo
Quiz #19: Using disable iff in a concurrent assertion	Internas	Passa sumo
Creating a Simple AXI-Lite Master for the Hexbus	Internas	Passa sumo
Envisioning the Ultimate I2C Controller	Internas	Passa sumo
Clock Gating	Internas	Passa sumo
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4	Internas	Passa sumo
Quiz #18: Failures in clocked immediate assertions	Internas	Passa sumo
AXI Handshaking Rules	Internas	Passa sumo
Measuring AXI latency and throughput performance	Internas	Passa sumo
Quiz #17: Induction failures	Internas	Passa sumo
The other half of the Gospel	Internas	Passa sumo
CPU based simulation, first thoughts	Internas	Passa sumo
Quiz #16: Immediate assertions in the presence of asynchronous resets	Internas	Passa sumo
Building a Better Verilog Multiply for the ZipCPU	Internas	Passa sumo
Examples of AXI4 bus masters	Internas	Passa sumo
Quiz #15: Pass-through memory	Internas	Passa sumo
Fixing Xilinx's Broken AXI-lite Design in VHDL	Internas	Passa sumo
Building a Simple AXI-lite Memory Controller	Internas	Passa sumo
Common AXI Themes on Xilinx's Forum	Internas	Passa sumo
Whatever happened to the ZipOS?	Internas	Passa sumo
Lessons learned while building an ASIC design	Internas	Passa sumo
The FPGA designer who didn't get the job	Internas	Passa sumo
Ultimate Logic	Internas	Passa sumo
Quiz #14: Two nearly identical frequencies	Internas	Passa sumo
Formally verifying register handling	Internas	Passa sumo
Is it possible to make a living as a solo digital design engineer?	Internas	Passa sumo
Spectrograms need Window Functions	Internas	Passa sumo
A fun Friday evening--verifying an AXI-lite slave	Internas	Passa sumo
Moving values and strobes cross clock domains	Internas	Passa sumo
Quiz #13: Temporal assertion equivalences	Internas	Passa sumo
Run length encoding an AXI stream	Internas	Passa sumo
Driving an output on both edges of the clock	Internas	Passa sumo
Building a Downsampling Filter	Internas	Passa sumo
I have a brand new piece of IP. How shall I verify it?	Internas	Passa sumo
Measuring clock speed	Internas	Passa sumo
The hard part of building a bursting AXI Master	Internas	Passa sumo
Four keys to getting your design to work the first time	Internas	Passa sumo
Quiz #12: Catching extraneous acknowledgments	Internas	Passa sumo
Building a Protocol Firewall	Internas	Passa sumo
Debugging AXI Streams	Internas	Passa sumo
Adding an AXI-Lite interface to your Verilator test script	Internas	Passa sumo
Re: What does your design flow look like?	Internas	Passa sumo
Building a basic AXI Master	Internas	Passa sumo
Cheap Spectral Estimation	Internas	Passa sumo
Locally resetting an AXI component	Internas	Passa sumo
Adjusting our logic PLL to handle I&Q	Internas	Passa sumo
Buidilng an AXI-Lite slave the easy way	Internas	Passa sumo
The Faith of a Mustard Seed	Internas	Passa sumo
A Histogram Gone Bad	Internas	Passa sumo
Quiz #11: Induction and clock enables	Internas	Passa sumo
Quiz #10: Checking stall conditions	Internas	Passa sumo
Lessons in Hardware Reuse	Internas	Passa sumo
2019: AXI Meets Formal Verification	Internas	Passa sumo
The Christmas Gospel	Internas	Passa sumo
Using a Histogram to Debug A/D Data Streams	Internas	Passa sumo
Quiz #9: Immediate assertions midst blocking assignments	Internas	Passa sumo
Quiz #8: Will this pass a bounded model check?	Internas	Passa sumo
The ZipCPU meets blinky	Internas	Passa sumo
Formally Verifying a General Purpose Ultra-Micro Controller	Internas	Passa sumo
Quiz #7: Returning to $past() and our counter again	Internas	Passa sumo
Putting the pieces together to build a data recorder	Internas	Passa sumo
Is formal verfication enough, or is simulation required?	Internas	Passa sumo
Quiz #6: Synchronous logic in Asynchronous contexts	Internas	Passa sumo
AXI Verification, the story so far	Internas	Passa sumo
Understanding AutoFPGA's address assignment algorithm	Internas	Passa sumo
Quiz #5: Immediate vs Concurrent Assertions	Internas	Passa sumo
Connecting lots of slaves to a bus without using a lot of logic	Internas	Passa sumo
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?	Internas	Passa sumo
Technology Debt and AutoFPGA, the bill just came due	Internas	Passa sumo
Xilinx deleted this post	Internas	Passa sumo
Quiz #3: Will formal verification prove this counter keeps its bounds?	Internas	Passa sumo
Planning an Intermediate Design Tutorial	Internas	Passa sumo
Quiz #2: Will this counter pass formal verification?	Internas	Passa sumo
Quiz #1: Will the assertion below ever fail?	Internas	Passa sumo
Just how long does a formal proof take to finish?	Internas	Passa sumo
Lessons learned while building crossbar interconnects	Internas	Passa sumo
Breaking all the rules to create an arbitrary clock signal	Internas	Passa sumo
Building the perfect AXI4 slave	Internas	Passa sumo
Building a Skid Buffer for AXI processing	Internas	Passa sumo
Examining Xilinx's AXI demonstration core	Internas	Passa sumo
Understanding AXI Addressing	Internas	Passa sumo
Project Ideas: PMod AMP2	Internas	Passa sumo
Applying Formal Methods to the Events of the Resurrection	Internas	Passa sumo
The most common AXI mistake	Internas	Passa sumo
The ZipCPU's Interrupt Controller	Internas	Passa sumo
Logic usage and decoding return results with cascaded multiplexers	Internas	Passa sumo
Building a universal QSPI flash controller	Internas	Passa sumo
Introducing the ArrowZip ZipCPU design, featuring the Max-1000	Internas	Passa sumo
Using Sequence Properties to Verify a Serial Port Transmitter	Internas	Passa sumo
Why does blinky make a CPU appear to be so slow?	Internas	Passa sumo
Debugging a CPU	Internas	Passa sumo
Building a custom yet functional AXI-lite slave	Internas	Passa sumo
ZipCPU highlights from 2018	Internas	Passa sumo
Using a formal property file to verify an AXI-lite peripheral	Internas	Passa sumo
AutoFPGA's linker script support gets an update	Internas	Passa sumo
Makefiles for formal proofs with SymbiYosys	Internas	Passa sumo
Swapping assumptions and assertions doesn't work	Internas	Passa sumo
Building a video controller: it's just a pair of counters	Internas	Passa sumo
Accessing the registers of a SoC+FPGA	Internas	Passa sumo
Taking a look at the TinyFPGA BX	Internas	Passa sumo
To my new readers and my new twitter followers, welcome!	Internas	Passa sumo
An Open Source Pipelined FFT Generator	Internas	Passa sumo
It's time for ORCONF 2018!	Internas	Passa sumo
My design works in simulation, but not in hardware. Can formal methods help me?	Internas	Passa sumo
Handling multiple clocks with Verilator	Internas	Passa sumo
RE: Building a simulation for my design? What does that mean?	Internas	Passa sumo
How to build a SPI Flash Controller for an FPGA	Internas	Passa sumo
Reasons why Synthesis might not match Simulation	Internas	Passa sumo
Why I like Formal: the ZipCPU and the ICO board	Internas	Passa sumo
What does Formal Development look like in Practice?	Internas	Passa sumo
Formally Verifying Memory and Cache Components	Internas	Passa sumo
Crossing clock domains with an Asynchronous FIFO	Internas	Passa sumo
Formally Verifying Asynchronous Components	Internas	Passa sumo
A Slow but Symmetric FIR Filter Implementation	Internas	Passa sumo
Updated Projects List	Internas	Passa sumo
Aggregating verified modules together	Internas	Passa sumo
ZipTimer: A simple countdown timer	Internas	Passa sumo
Formally Verifying an Asynchronous Reset	Internas	Passa sumo
What would you like to see on the ZipCPU blog?	Internas	Passa sumo
Will formal methods ever find a bug in a working CPU?	Internas	Passa sumo
Resurrection Day!	Internas	Passa sumo
Quadratic fits are entirely inappropriate for DSP	Internas	Passa sumo
Pipelining a Prefetch	Internas	Passa sumo
Is formal really all that hard?	Internas	Passa sumo
An Exercise in using Formal Induction	Internas	Passa sumo
Want to use ZBasic? Let's have some fun--no actual FPGA required!	Internas	Passa sumo
Debugging a Cyclone-V	Internas	Passa sumo
ZipCPU toolchain and initial test	Internas	Passa sumo
Updating ZipCPU files	Internas	Passa sumo
Interpolation is just a special type of convolution	Internas	Passa sumo
A Quick Introduction to the ZipCPU Instruction Set	Internas	Passa sumo
Top 10 ZipCPU blog posts for 2017	Internas	Passa sumo
A better filter implementation for slower signals	Internas	Passa sumo
Mystery post: The ugliest bug I've ever encountered	Internas	Passa sumo
Arrow's Max-1000: A gem for all the wrong reasons	Internas	Passa sumo
Building a Simple Logic PLL	Internas	Passa sumo
Building a Numerically Controlled Oscillator	Internas	Passa sumo
Testing the fast, generic FIR filter	Internas	Passa sumo
Thank you!	Internas	Passa sumo
Measuring the frequency response of a filter under test	Internas	Passa sumo
Building a prefetch module for the ZipCPU	Internas	Passa sumo
Generating more than one bit at a time with an LFSR	Internas	Passa sumo
An example LFSR	Internas	Passa sumo
A Configurable Signal Delay Element	Internas	Passa sumo
Building Formal Assumptions to Describe Wishbone Behaviour	Internas	Passa sumo
The Interface to a Generic Filtering Testbench	Internas	Passa sumo
Good Software Engineering Principles Apply to Students Too	Internas	Passa sumo
Generating Pseudo-Random Numbers on an FPGA	Internas	Passa sumo
Some Simple Clock-Domain Crossing Solutions	Internas	Passa sumo
My first experience with Formal Methods	Internas	Passa sumo
Just some notes to new readers of the ZipCPU blog	Internas	Passa sumo
Implementing the Moving Average (Boxcar) filter	Internas	Passa sumo
FPGAs vs ASICs	Internas	Passa sumo
It's all about the interfaces	Internas	Passa sumo
Using AutoFPGA to connect simple registers to a debugging bus	Internas	Passa sumo
A Brief Introduction to AutoFPGA	Internas	Passa sumo
A CORDIC testbench	Internas	Passa sumo
A Cheaper Fast FIR Filter	Internas	Passa sumo
Understanding the effects of Quantization	Internas	Passa sumo
Clocks for Software Engineers	Internas	Passa sumo
Demonstrating the improved PWM waveform	Internas	Passa sumo
Building a high speed Finite Impulse Response (FIR) Digital Filter	Internas	Passa sumo
Even I get stuck in FPGA Hell	Internas	Passa sumo
Glad I went to ORCONF	Internas	Passa sumo
Off to ORCONF-2017!	Internas	Passa sumo
Reinventing PWM	Internas	Passa sumo
Big Money Engineering Integrity	Internas	Passa sumo
CORDIC part two: rectangular to polar conversion	Internas	Passa sumo
Using a CORDIC to calculate sines and cosines in an FPGA	Internas	Passa sumo
Building a quarter sine-wave lookup table	Internas	Passa sumo
Debugging your soft-core CPU within an FPGA	Internas	Passa sumo
The ZipCPU's pipeline logic	Internas	Passa sumo
Rules for new FPGA designers	Internas	Passa sumo
Two of the Simplest Digital filters	Internas	Passa sumo
Strategies for pipelining logic	Internas	Passa sumo
What would cause you to lie?	Internas	Passa sumo
A Simple ALU, drawn from the ZipCPU	Internas	Passa sumo
Series: Debouncing in Digital Logic	Internas	Passa sumo
Using a debug-bus to Measure Bouncing	Internas	Passa sumo
Measuring Contact Bounce	Internas	Passa sumo
How to eliminate button bounces with digital logic	Internas	Passa sumo
Visualizing Contact Bounce	Internas	Passa sumo
ZipCPU Advertising	Internas	Passa sumo
Writing your own VCD File	Internas	Passa sumo
Linear Interpolation	Internas	Passa sumo
Getting the basic FIFO right	Internas	Passa sumo
Windows FPGA designers may not need a Linux machine ... yet	Internas	Passa sumo
How to build a simulation based debugger for your own soft-core CPU	Internas	Passa sumo
How to Debug a DSP algorithm	Internas	Passa sumo
Rounding Numbers without Adding a Bias	Internas	Passa sumo
Bit growth in FPGA arithmetic	Internas	Passa sumo
A Basic Upsampling Linear Interpolator	Internas	Passa sumo
Verilator doesn't find everything (today)	Internas	Passa sumo
Design Needs when Debugging a SoftCore CPU	Internas	Passa sumo
The simplest sine wave generator within an FPGA	Internas	Passa sumo
Getting Started with the Wishbone Scope	Internas	Passa sumo
Finishing off the debugging bus: building a software interface	Internas	Passa sumo
Why you want a debug port into your FPGA	Internas	Passa sumo
Simulating an FPGA through the debugging interface	Internas	Passa sumo
My own FPGA debugging philosophy	Internas	Passa sumo
Building a very simple wishbone interconnect	Internas	Passa sumo
Taking a New Look at Verilator	Internas	Passa sumo
Putting our Debugging Bus RTL Components Together	Internas	Passa sumo
Sending bus idle notifications down the line	Internas	Passa sumo
Why Use a Network Interface to your FPGA	Internas	Passa sumo
Support me on Patreon	Internas	Passa sumo
The debugging bus: a goal for FPGA interaction	Internas	Passa sumo
Adding interrupt reporting to our debugging bus	Internas	Passa sumo
How to send our bus results back out the serial port	Internas	Passa sumo
No PI for you	Internas	Passa sumo
How to create bus command words, from a 7-bit data stream	Internas	Passa sumo
Minimizing FPGA Resource Utilization	Internas	Passa sumo
A College Student's Response to the FPGA Design Process	Internas	Passa sumo
Building a Simple Wishbone Master	Internas	Passa sumo
Building A Simple In-Circuit Logic Analyzer	Internas	Passa sumo
Nearest Neighbor Interpolation	Internas	Passa sumo
An Overview of a Wishbone-UART Bridge	Internas	Passa sumo
Campus Sidewalks and FPGA Design	Internas	Passa sumo
Controlling Timing within an FPGA	Internas	Passa sumo
The Actual FPGA Design Process	Internas	Passa sumo
Building a simple wishbone slave	Internas	Passa sumo
Bus Select Lines	Internas	Passa sumo
FFT debugging	Internas	Passa sumo
Debugging an FPGA through the serial port--first steps	Internas	Passa sumo
That first serial port: Debugging when you are blind	Internas	Passa sumo
Building a simple bus	Internas	Passa sumo
Moving to memory	Internas	Passa sumo
A Vision for Controlling FPGA Logic	Internas	Passa sumo
Which comes first: the CPU or the peripherals?	Internas	Passa sumo
Knight Rider	Internas	Passa sumo
FPGA Hell	Internas	Passa sumo
Blinky	Internas	Passa sumo
Most common Digilent FPGA support requests	Internas	Passa sumo
Cannot be done	Internas	Passa sumo
Welcome to the ZipCPU blog!	Internas	Passa sumo
via RSS	Internas	Passa sumo

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