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The ZipCPU by Gisselquist Technology

Gegenereerd op Mei 03 2026 13:40 PM

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The ZipCPU by Gisselquist Technology

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The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

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Headings

H1	H2	H3	H4	H5	H6
1	270	0	0	0	0

[H1] Blog Posts
[H2] Device Clock Generation
[H2] Quiz #24: Is there an AXI bug here?
[H2] Comparing the Xilinx MIG with an open source DDR3 controller
[H2] Wrap addressing
[H2] Your problem is not AXI
[H2] My Personal Journey in Verification
[H2] Debugging video from across the ocean
[H2] Bringing up Kimos
[H2] Chasing resets
[H2] 2023, Year in review
[H2] An Overview of a 10Gb Ethernet Switch
[H2] SDIO RX: Bugs found w/ Formal methods
[H2] Using a Verilog task to simulate a packet generator for an SDIO controller
[H2] Introducing the ZipCPU v3.0
[H2] What is a Virtual Packet FIFO?
[H2] What is a SwiC?
[H2] Debugging the Hard Stuff
[H2] Your soft-core CPU won't boot. Where should you start debugging?
[H2] Thanksgiving! I have much to be thankful for
[H2] Quiz #23: Can this assertion fail?
[H2] A first lesson in sales pitches: Honesty
[H2] Quiz #22: Handling cover failures
[H2] Measuring the Steps to Design Checkoff
[H2] Assignment delay's and Verilog's wait statement
[H2] It's not my fault! Your code is broken.
[H2] Protocol Design for Network Debugging
[H2] Quiz #21: Verifying all configurations of a design
[H2] ZipCPU Lesson: If it's not tested, it doesn't work.
[H2] A Coming Economic Downturn? or Worse?
[H2] Quiz #20: Using $stable in a multiclock environment
[H2] Learning AXI: Where to start?
[H2] Bringing up a new piece of hardware -- what can go wrong?
[H2] Rethinking Video with AXI video streams
[H2] AXI Stream is broken
[H2] 2020 and 2021 in review
[H2] Quiz #19: Using disable iff in a concurrent assertion
[H2] Creating a Simple AXI-Lite Master for the Hexbus
[H2] Envisioning the Ultimate I2C Controller
[H2] Clock Gating
[H2] Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
[H2] Quiz #18: Failures in clocked immediate assertions
[H2] AXI Handshaking Rules
[H2] Measuring AXI latency and throughput performance
[H2] Quiz #17: Induction failures
[H2] The other half of the Gospel
[H2] CPU based simulation, first thoughts
[H2] Quiz #16: Immediate assertions in the presence of asynchronous resets
[H2] Building a Better Verilog Multiply for the ZipCPU
[H2] Examples of AXI4 bus masters
[H2] Quiz #15: Pass-through memory
[H2] Fixing Xilinx's Broken AXI-lite Design in VHDL
[H2] Building a Simple AXI-lite Memory Controller
[H2] Common AXI Themes on Xilinx's Forum
[H2] Whatever happened to the ZipOS?
[H2] Lessons learned while building an ASIC design
[H2] The FPGA designer who didn't get the job
[H2] Ultimate Logic
[H2] Quiz #14: Two nearly identical frequencies
[H2] Formally verifying register handling
[H2] Is it possible to make a living as a solo digital design engineer?
[H2] Spectrograms need Window Functions
[H2] A fun Friday evening--verifying an AXI-lite slave
[H2] Moving values and strobes cross clock domains
[H2] Quiz #13: Temporal assertion equivalences
[H2] Run length encoding an AXI stream
[H2] Driving an output on both edges of the clock
[H2] Building a Downsampling Filter
[H2] I have a brand new piece of IP. How shall I verify it?
[H2] Measuring clock speed
[H2] The hard part of building a bursting AXI Master
[H2] Four keys to getting your design to work the first time
[H2] Quiz #12: Catching extraneous acknowledgments
[H2] Building a Protocol Firewall
[H2] Debugging AXI Streams
[H2] Adding an AXI-Lite interface to your Verilator test script
[H2] Re: What does your design flow look like?
[H2] Building a basic AXI Master
[H2] Cheap Spectral Estimation
[H2] Locally resetting an AXI component
[H2] Adjusting our logic PLL to handle I&Q
[H2] Buidilng an AXI-Lite slave the easy way
[H2] The Faith of a Mustard Seed
[H2] A Histogram Gone Bad
[H2] Quiz #11: Induction and clock enables
[H2] Quiz #10: Checking stall conditions
[H2] Lessons in Hardware Reuse
[H2] 2019: AXI Meets Formal Verification
[H2] The Christmas Gospel
[H2] Using a Histogram to Debug A/D Data Streams
[H2] Quiz #9: Immediate assertions midst blocking assignments
[H2] Quiz #8: Will this pass a bounded model check?
[H2] The ZipCPU meets blinky
[H2] Formally Verifying a General Purpose Ultra-Micro Controller
[H2] Quiz #7: Returning to $past() and our counter again
[H2] Putting the pieces together to build a data recorder
[H2] Is formal verfication enough, or is simulation required?
[H2] Quiz #6: Synchronous logic in Asynchronous contexts
[H2] AXI Verification, the story so far
[H2] Understanding AutoFPGA's address assignment algorithm
[H2] Quiz #5: Immediate vs Concurrent Assertions
[H2] Connecting lots of slaves to a bus without using a lot of logic
[H2] Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
[H2] Technology Debt and AutoFPGA, the bill just came due
[H2] Xilinx deleted this post
[H2] Quiz #3: Will formal verification prove this counter keeps its bounds?
[H2] Planning an Intermediate Design Tutorial
[H2] Quiz #2: Will this counter pass formal verification?
[H2] Quiz #1: Will the assertion below ever fail?
[H2] Just how long does a formal proof take to finish?
[H2] Lessons learned while building crossbar interconnects
[H2] Breaking all the rules to create an arbitrary clock signal
[H2] Building the perfect AXI4 slave
[H2] Building a Skid Buffer for AXI processing
[H2] Examining Xilinx's AXI demonstration core
[H2] Understanding AXI Addressing
[H2] Project Ideas: PMod AMP2
[H2] Applying Formal Methods to the Events of the Resurrection
[H2] The most common AXI mistake
[H2] The ZipCPU's Interrupt Controller
[H2] Logic usage and decoding return results with cascaded multiplexers
[H2] Building a universal QSPI flash controller
[H2] Introducing the ArrowZip ZipCPU design, featuring the Max-1000
[H2] Using Sequence Properties to Verify a Serial Port Transmitter
[H2] Why does blinky make a CPU appear to be so slow?
[H2] Debugging a CPU
[H2] Building a custom yet functional AXI-lite slave
[H2] ZipCPU highlights from 2018
[H2] Using a formal property file to verify an AXI-lite peripheral
[H2] AutoFPGA's linker script support gets an update
[H2] Makefiles for formal proofs with SymbiYosys
[H2] Swapping assumptions and assertions doesn't work
[H2] Building a video controller: it's just a pair of counters
[H2] Accessing the registers of a SoC+FPGA
[H2] Taking a look at the TinyFPGA BX
[H2] To my new readers and my new twitter followers, welcome!
[H2] An Open Source Pipelined FFT Generator
[H2] It's time for ORCONF 2018!
[H2] My design works in simulation, but not in hardware. Can formal methods help me?
[H2] Handling multiple clocks with Verilator
[H2] RE: Building a simulation for my design? What does that mean?
[H2] How to build a SPI Flash Controller for an FPGA
[H2] Reasons why Synthesis might not match Simulation
[H2] Why I like Formal: the ZipCPU and the ICO board
[H2] What does Formal Development look like in Practice?
[H2] Formally Verifying Memory and Cache Components
[H2] Crossing clock domains with an Asynchronous FIFO
[H2] Formally Verifying Asynchronous Components
[H2] A Slow but Symmetric FIR Filter Implementation
[H2] Updated Projects List
[H2] Aggregating verified modules together
[H2] ZipTimer: A simple countdown timer
[H2] Formally Verifying an Asynchronous Reset
[H2] What would you like to see on the ZipCPU blog?
[H2] Will formal methods ever find a bug in a working CPU?
[H2] Resurrection Day!
[H2] Quadratic fits are entirely inappropriate for DSP
[H2] Pipelining a Prefetch
[H2] Is formal really all that hard?
[H2] An Exercise in using Formal Induction
[H2] Want to use ZBasic? Let's have some fun--no actual FPGA required!
[H2] Debugging a Cyclone-V
[H2] ZipCPU toolchain and initial test
[H2] Updating ZipCPU files
[H2] Interpolation is just a special type of convolution
[H2] A Quick Introduction to the ZipCPU Instruction Set
[H2] Top 10 ZipCPU blog posts for 2017
[H2] A better filter implementation for slower signals
[H2] Mystery post: The ugliest bug I've ever encountered
[H2] Arrow's Max-1000: A gem for all the wrong reasons
[H2] Building a Simple Logic PLL
[H2] Building a Numerically Controlled Oscillator
[H2] Testing the fast, generic FIR filter
[H2] Thank you!
[H2] Measuring the frequency response of a filter under test
[H2] Building a prefetch module for the ZipCPU
[H2] Generating more than one bit at a time with an LFSR
[H2] An example LFSR
[H2] A Configurable Signal Delay Element
[H2] Building Formal Assumptions to Describe Wishbone Behaviour
[H2] The Interface to a Generic Filtering Testbench
[H2] Good Software Engineering Principles Apply to Students Too
[H2] Generating Pseudo-Random Numbers on an FPGA
[H2] Some Simple Clock-Domain Crossing Solutions
[H2] My first experience with Formal Methods
[H2] Just some notes to new readers of the ZipCPU blog
[H2] Implementing the Moving Average (Boxcar) filter
[H2] FPGAs vs ASICs
[H2] It's all about the interfaces
[H2] Using AutoFPGA to connect simple registers to a debugging bus
[H2] A Brief Introduction to AutoFPGA
[H2] A CORDIC testbench
[H2] A Cheaper Fast FIR Filter
[H2] Understanding the effects of Quantization
[H2] Clocks for Software Engineers
[H2] Demonstrating the improved PWM waveform
[H2] Building a high speed Finite Impulse Response (FIR) Digital Filter
[H2] Even I get stuck in FPGA Hell
[H2] Glad I went to ORCONF
[H2] Off to ORCONF-2017!
[H2] Reinventing PWM
[H2] Big Money Engineering Integrity
[H2] CORDIC part two: rectangular to polar conversion
[H2] Using a CORDIC to calculate sines and cosines in an FPGA
[H2] Building a quarter sine-wave lookup table
[H2] Debugging your soft-core CPU within an FPGA
[H2] The ZipCPU's pipeline logic
[H2] Rules for new FPGA designers
[H2] Two of the Simplest Digital filters
[H2] Strategies for pipelining logic
[H2] What would cause you to lie?
[H2] A Simple ALU, drawn from the ZipCPU
[H2] Series: Debouncing in Digital Logic
[H2] Using a debug-bus to Measure Bouncing
[H2] Measuring Contact Bounce
[H2] How to eliminate button bounces with digital logic
[H2] Visualizing Contact Bounce
[H2] ZipCPU Advertising
[H2] Writing your own VCD File
[H2] Linear Interpolation
[H2] Getting the basic FIFO right
[H2] Windows FPGA designers may not need a Linux machine ... yet
[H2] How to build a simulation based debugger for your own soft-core CPU
[H2] How to Debug a DSP algorithm
[H2] Rounding Numbers without Adding a Bias
[H2] Bit growth in FPGA arithmetic
[H2] A Basic Upsampling Linear Interpolator
[H2] Verilator doesn't find everything (today)
[H2] Design Needs when Debugging a SoftCore CPU
[H2] The simplest sine wave generator within an FPGA
[H2] Getting Started with the Wishbone Scope
[H2] Finishing off the debugging bus: building a software interface
[H2] Why you want a debug port into your FPGA
[H2] Simulating an FPGA through the debugging interface
[H2] My own FPGA debugging philosophy
[H2] Building a very simple wishbone interconnect
[H2] Taking a New Look at Verilator
[H2] Putting our Debugging Bus RTL Components Together
[H2] Sending bus idle notifications down the line
[H2] Why Use a Network Interface to your FPGA
[H2] Support me on Patreon
[H2] The debugging bus: a goal for FPGA interaction
[H2] Adding interrupt reporting to our debugging bus
[H2] How to send our bus results back out the serial port
[H2] No PI for you
[H2] How to create bus command words, from a 7-bit data stream
[H2] Minimizing FPGA Resource Utilization
[H2] A College Student's Response to the FPGA Design Process
[H2] Building a Simple Wishbone Master
[H2] Building A Simple In-Circuit Logic Analyzer
[H2] Nearest Neighbor Interpolation
[H2] An Overview of a Wishbone-UART Bridge
[H2] Campus Sidewalks and FPGA Design
[H2] Controlling Timing within an FPGA
[H2] The Actual FPGA Design Process
[H2] Building a simple wishbone slave
[H2] Bus Select Lines
[H2] FFT debugging
[H2] Debugging an FPGA through the serial port--first steps
[H2] That first serial port: Debugging when you are blind
[H2] Building a simple bus
[H2] Moving to memory
[H2] A Vision for Controlling FPGA Logic
[H2] Which comes first: the CPU or the peripherals?
[H2] Knight Rider
[H2] FPGA Hell
[H2] Blinky
[H2] Most common Digilent FPGA support requests
[H2] Cannot be done
[H2] Welcome to the ZipCPU blog!
[H2] The ZipCPU by Gisselquist Technology

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Ankertekst	Type	samenstelling
About Us	Intern	doFollow
FPGA Hell	Intern	doFollow
Tutorial	Intern	doFollow
Formal training	Intern	doFollow
Quizzes	Intern	doFollow
Projects	Intern	doFollow
Site Index	Intern	doFollow
Device Clock Generation	Intern	doFollow
Quiz #24: Is there an AXI bug here?	Intern	doFollow
Comparing the Xilinx MIG with an open source DDR3 controller	Intern	doFollow
Wrap addressing	Intern	doFollow
Your problem is not AXI	Intern	doFollow
My Personal Journey in Verification	Intern	doFollow
Debugging video from across the ocean	Intern	doFollow
Bringing up Kimos	Intern	doFollow
Chasing resets	Intern	doFollow
2023, Year in review	Intern	doFollow
An Overview of a 10Gb Ethernet Switch	Intern	doFollow
SDIO RX: Bugs found w/ Formal methods	Intern	doFollow
Using a Verilog task to simulate a packet generator for an SDIO controller	Intern	doFollow
Introducing the ZipCPU v3.0	Intern	doFollow
What is a Virtual Packet FIFO?	Intern	doFollow
What is a SwiC?	Intern	doFollow
Debugging the Hard Stuff	Intern	doFollow
Your soft-core CPU won't boot. Where should you start debugging?	Intern	doFollow
Thanksgiving! I have much to be thankful for	Intern	doFollow
Quiz #23: Can this assertion fail?	Intern	doFollow
A first lesson in sales pitches: Honesty	Intern	doFollow
Quiz #22: Handling cover failures	Intern	doFollow
Measuring the Steps to Design Checkoff	Intern	doFollow
Assignment delay's and Verilog's wait statement	Intern	doFollow
It's not my fault! Your code is broken.	Intern	doFollow
Protocol Design for Network Debugging	Intern	doFollow
Quiz #21: Verifying all configurations of a design	Intern	doFollow
ZipCPU Lesson: If it's not tested, it doesn't work.	Intern	doFollow
A Coming Economic Downturn? or Worse?	Intern	doFollow
Quiz #20: Using $stable in a multiclock environment	Intern	doFollow
Learning AXI: Where to start?	Intern	doFollow
Bringing up a new piece of hardware -- what can go wrong?	Intern	doFollow
Rethinking Video with AXI video streams	Intern	doFollow
AXI Stream is broken	Intern	doFollow
2020 and 2021 in review	Intern	doFollow
Quiz #19: Using disable iff in a concurrent assertion	Intern	doFollow
Creating a Simple AXI-Lite Master for the Hexbus	Intern	doFollow
Envisioning the Ultimate I2C Controller	Intern	doFollow
Clock Gating	Intern	doFollow
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4	Intern	doFollow
Quiz #18: Failures in clocked immediate assertions	Intern	doFollow
AXI Handshaking Rules	Intern	doFollow
Measuring AXI latency and throughput performance	Intern	doFollow
Quiz #17: Induction failures	Intern	doFollow
The other half of the Gospel	Intern	doFollow
CPU based simulation, first thoughts	Intern	doFollow
Quiz #16: Immediate assertions in the presence of asynchronous resets	Intern	doFollow
Building a Better Verilog Multiply for the ZipCPU	Intern	doFollow
Examples of AXI4 bus masters	Intern	doFollow
Quiz #15: Pass-through memory	Intern	doFollow
Fixing Xilinx's Broken AXI-lite Design in VHDL	Intern	doFollow
Building a Simple AXI-lite Memory Controller	Intern	doFollow
Common AXI Themes on Xilinx's Forum	Intern	doFollow
Whatever happened to the ZipOS?	Intern	doFollow
Lessons learned while building an ASIC design	Intern	doFollow
The FPGA designer who didn't get the job	Intern	doFollow
Ultimate Logic	Intern	doFollow
Quiz #14: Two nearly identical frequencies	Intern	doFollow
Formally verifying register handling	Intern	doFollow
Is it possible to make a living as a solo digital design engineer?	Intern	doFollow
Spectrograms need Window Functions	Intern	doFollow
A fun Friday evening--verifying an AXI-lite slave	Intern	doFollow
Moving values and strobes cross clock domains	Intern	doFollow
Quiz #13: Temporal assertion equivalences	Intern	doFollow
Run length encoding an AXI stream	Intern	doFollow
Driving an output on both edges of the clock	Intern	doFollow
Building a Downsampling Filter	Intern	doFollow
I have a brand new piece of IP. How shall I verify it?	Intern	doFollow
Measuring clock speed	Intern	doFollow
The hard part of building a bursting AXI Master	Intern	doFollow
Four keys to getting your design to work the first time	Intern	doFollow
Quiz #12: Catching extraneous acknowledgments	Intern	doFollow
Building a Protocol Firewall	Intern	doFollow
Debugging AXI Streams	Intern	doFollow
Adding an AXI-Lite interface to your Verilator test script	Intern	doFollow
Re: What does your design flow look like?	Intern	doFollow
Building a basic AXI Master	Intern	doFollow
Cheap Spectral Estimation	Intern	doFollow
Locally resetting an AXI component	Intern	doFollow
Adjusting our logic PLL to handle I&Q	Intern	doFollow
Buidilng an AXI-Lite slave the easy way	Intern	doFollow
The Faith of a Mustard Seed	Intern	doFollow
A Histogram Gone Bad	Intern	doFollow
Quiz #11: Induction and clock enables	Intern	doFollow
Quiz #10: Checking stall conditions	Intern	doFollow
Lessons in Hardware Reuse	Intern	doFollow
2019: AXI Meets Formal Verification	Intern	doFollow
The Christmas Gospel	Intern	doFollow
Using a Histogram to Debug A/D Data Streams	Intern	doFollow
Quiz #9: Immediate assertions midst blocking assignments	Intern	doFollow
Quiz #8: Will this pass a bounded model check?	Intern	doFollow
The ZipCPU meets blinky	Intern	doFollow
Formally Verifying a General Purpose Ultra-Micro Controller	Intern	doFollow
Quiz #7: Returning to $past() and our counter again	Intern	doFollow
Putting the pieces together to build a data recorder	Intern	doFollow
Is formal verfication enough, or is simulation required?	Intern	doFollow
Quiz #6: Synchronous logic in Asynchronous contexts	Intern	doFollow
AXI Verification, the story so far	Intern	doFollow
Understanding AutoFPGA's address assignment algorithm	Intern	doFollow
Quiz #5: Immediate vs Concurrent Assertions	Intern	doFollow
Connecting lots of slaves to a bus without using a lot of logic	Intern	doFollow
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?	Intern	doFollow
Technology Debt and AutoFPGA, the bill just came due	Intern	doFollow
Xilinx deleted this post	Intern	doFollow
Quiz #3: Will formal verification prove this counter keeps its bounds?	Intern	doFollow
Planning an Intermediate Design Tutorial	Intern	doFollow
Quiz #2: Will this counter pass formal verification?	Intern	doFollow
Quiz #1: Will the assertion below ever fail?	Intern	doFollow
Just how long does a formal proof take to finish?	Intern	doFollow
Lessons learned while building crossbar interconnects	Intern	doFollow
Breaking all the rules to create an arbitrary clock signal	Intern	doFollow
Building the perfect AXI4 slave	Intern	doFollow
Building a Skid Buffer for AXI processing	Intern	doFollow
Examining Xilinx's AXI demonstration core	Intern	doFollow
Understanding AXI Addressing	Intern	doFollow
Project Ideas: PMod AMP2	Intern	doFollow
Applying Formal Methods to the Events of the Resurrection	Intern	doFollow
The most common AXI mistake	Intern	doFollow
The ZipCPU's Interrupt Controller	Intern	doFollow
Logic usage and decoding return results with cascaded multiplexers	Intern	doFollow
Building a universal QSPI flash controller	Intern	doFollow
Introducing the ArrowZip ZipCPU design, featuring the Max-1000	Intern	doFollow
Using Sequence Properties to Verify a Serial Port Transmitter	Intern	doFollow
Why does blinky make a CPU appear to be so slow?	Intern	doFollow
Debugging a CPU	Intern	doFollow
Building a custom yet functional AXI-lite slave	Intern	doFollow
ZipCPU highlights from 2018	Intern	doFollow
Using a formal property file to verify an AXI-lite peripheral	Intern	doFollow
AutoFPGA's linker script support gets an update	Intern	doFollow
Makefiles for formal proofs with SymbiYosys	Intern	doFollow
Swapping assumptions and assertions doesn't work	Intern	doFollow
Building a video controller: it's just a pair of counters	Intern	doFollow
Accessing the registers of a SoC+FPGA	Intern	doFollow
Taking a look at the TinyFPGA BX	Intern	doFollow
To my new readers and my new twitter followers, welcome!	Intern	doFollow
An Open Source Pipelined FFT Generator	Intern	doFollow
It's time for ORCONF 2018!	Intern	doFollow
My design works in simulation, but not in hardware. Can formal methods help me?	Intern	doFollow
Handling multiple clocks with Verilator	Intern	doFollow
RE: Building a simulation for my design? What does that mean?	Intern	doFollow
How to build a SPI Flash Controller for an FPGA	Intern	doFollow
Reasons why Synthesis might not match Simulation	Intern	doFollow
Why I like Formal: the ZipCPU and the ICO board	Intern	doFollow
What does Formal Development look like in Practice?	Intern	doFollow
Formally Verifying Memory and Cache Components	Intern	doFollow
Crossing clock domains with an Asynchronous FIFO	Intern	doFollow
Formally Verifying Asynchronous Components	Intern	doFollow
A Slow but Symmetric FIR Filter Implementation	Intern	doFollow
Updated Projects List	Intern	doFollow
Aggregating verified modules together	Intern	doFollow
ZipTimer: A simple countdown timer	Intern	doFollow
Formally Verifying an Asynchronous Reset	Intern	doFollow
What would you like to see on the ZipCPU blog?	Intern	doFollow
Will formal methods ever find a bug in a working CPU?	Intern	doFollow
Resurrection Day!	Intern	doFollow
Quadratic fits are entirely inappropriate for DSP	Intern	doFollow
Pipelining a Prefetch	Intern	doFollow
Is formal really all that hard?	Intern	doFollow
An Exercise in using Formal Induction	Intern	doFollow
Want to use ZBasic? Let's have some fun--no actual FPGA required!	Intern	doFollow
Debugging a Cyclone-V	Intern	doFollow
ZipCPU toolchain and initial test	Intern	doFollow
Updating ZipCPU files	Intern	doFollow
Interpolation is just a special type of convolution	Intern	doFollow
A Quick Introduction to the ZipCPU Instruction Set	Intern	doFollow
Top 10 ZipCPU blog posts for 2017	Intern	doFollow
A better filter implementation for slower signals	Intern	doFollow
Mystery post: The ugliest bug I've ever encountered	Intern	doFollow
Arrow's Max-1000: A gem for all the wrong reasons	Intern	doFollow
Building a Simple Logic PLL	Intern	doFollow
Building a Numerically Controlled Oscillator	Intern	doFollow
Testing the fast, generic FIR filter	Intern	doFollow
Thank you!	Intern	doFollow
Measuring the frequency response of a filter under test	Intern	doFollow
Building a prefetch module for the ZipCPU	Intern	doFollow
Generating more than one bit at a time with an LFSR	Intern	doFollow
An example LFSR	Intern	doFollow
A Configurable Signal Delay Element	Intern	doFollow
Building Formal Assumptions to Describe Wishbone Behaviour	Intern	doFollow
The Interface to a Generic Filtering Testbench	Intern	doFollow
Good Software Engineering Principles Apply to Students Too	Intern	doFollow
Generating Pseudo-Random Numbers on an FPGA	Intern	doFollow
Some Simple Clock-Domain Crossing Solutions	Intern	doFollow
My first experience with Formal Methods	Intern	doFollow
Just some notes to new readers of the ZipCPU blog	Intern	doFollow
Implementing the Moving Average (Boxcar) filter	Intern	doFollow
FPGAs vs ASICs	Intern	doFollow
It's all about the interfaces	Intern	doFollow
Using AutoFPGA to connect simple registers to a debugging bus	Intern	doFollow
A Brief Introduction to AutoFPGA	Intern	doFollow
A CORDIC testbench	Intern	doFollow
A Cheaper Fast FIR Filter	Intern	doFollow
Understanding the effects of Quantization	Intern	doFollow
Clocks for Software Engineers	Intern	doFollow
Demonstrating the improved PWM waveform	Intern	doFollow
Building a high speed Finite Impulse Response (FIR) Digital Filter	Intern	doFollow
Even I get stuck in FPGA Hell	Intern	doFollow
Glad I went to ORCONF	Intern	doFollow
Off to ORCONF-2017!	Intern	doFollow
Reinventing PWM	Intern	doFollow
Big Money Engineering Integrity	Intern	doFollow
CORDIC part two: rectangular to polar conversion	Intern	doFollow
Using a CORDIC to calculate sines and cosines in an FPGA	Intern	doFollow
Building a quarter sine-wave lookup table	Intern	doFollow
Debugging your soft-core CPU within an FPGA	Intern	doFollow
The ZipCPU's pipeline logic	Intern	doFollow
Rules for new FPGA designers	Intern	doFollow
Two of the Simplest Digital filters	Intern	doFollow
Strategies for pipelining logic	Intern	doFollow
What would cause you to lie?	Intern	doFollow
A Simple ALU, drawn from the ZipCPU	Intern	doFollow
Series: Debouncing in Digital Logic	Intern	doFollow
Using a debug-bus to Measure Bouncing	Intern	doFollow
Measuring Contact Bounce	Intern	doFollow
How to eliminate button bounces with digital logic	Intern	doFollow
Visualizing Contact Bounce	Intern	doFollow
ZipCPU Advertising	Intern	doFollow
Writing your own VCD File	Intern	doFollow
Linear Interpolation	Intern	doFollow
Getting the basic FIFO right	Intern	doFollow
Windows FPGA designers may not need a Linux machine ... yet	Intern	doFollow
How to build a simulation based debugger for your own soft-core CPU	Intern	doFollow
How to Debug a DSP algorithm	Intern	doFollow
Rounding Numbers without Adding a Bias	Intern	doFollow
Bit growth in FPGA arithmetic	Intern	doFollow
A Basic Upsampling Linear Interpolator	Intern	doFollow
Verilator doesn't find everything (today)	Intern	doFollow
Design Needs when Debugging a SoftCore CPU	Intern	doFollow
The simplest sine wave generator within an FPGA	Intern	doFollow
Getting Started with the Wishbone Scope	Intern	doFollow
Finishing off the debugging bus: building a software interface	Intern	doFollow
Why you want a debug port into your FPGA	Intern	doFollow
Simulating an FPGA through the debugging interface	Intern	doFollow
My own FPGA debugging philosophy	Intern	doFollow
Building a very simple wishbone interconnect	Intern	doFollow
Taking a New Look at Verilator	Intern	doFollow
Putting our Debugging Bus RTL Components Together	Intern	doFollow
Sending bus idle notifications down the line	Intern	doFollow
Why Use a Network Interface to your FPGA	Intern	doFollow
Support me on Patreon	Intern	doFollow
The debugging bus: a goal for FPGA interaction	Intern	doFollow
Adding interrupt reporting to our debugging bus	Intern	doFollow
How to send our bus results back out the serial port	Intern	doFollow
No PI for you	Intern	doFollow
How to create bus command words, from a 7-bit data stream	Intern	doFollow
Minimizing FPGA Resource Utilization	Intern	doFollow
A College Student's Response to the FPGA Design Process	Intern	doFollow
Building a Simple Wishbone Master	Intern	doFollow
Building A Simple In-Circuit Logic Analyzer	Intern	doFollow
Nearest Neighbor Interpolation	Intern	doFollow
An Overview of a Wishbone-UART Bridge	Intern	doFollow
Campus Sidewalks and FPGA Design	Intern	doFollow
Controlling Timing within an FPGA	Intern	doFollow
The Actual FPGA Design Process	Intern	doFollow
Building a simple wishbone slave	Intern	doFollow
Bus Select Lines	Intern	doFollow
FFT debugging	Intern	doFollow
Debugging an FPGA through the serial port--first steps	Intern	doFollow
That first serial port: Debugging when you are blind	Intern	doFollow
Building a simple bus	Intern	doFollow
Moving to memory	Intern	doFollow
A Vision for Controlling FPGA Logic	Intern	doFollow
Which comes first: the CPU or the peripherals?	Intern	doFollow
Knight Rider	Intern	doFollow
FPGA Hell	Intern	doFollow
Blinky	Intern	doFollow
Most common Digilent FPGA support requests	Intern	doFollow
Cannot be done	Intern	doFollow
Welcome to the ZipCPU blog!	Intern	doFollow
via RSS	Intern	doFollow

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