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The ZipCPU by Gisselquist Technology

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The ZipCPU by Gisselquist Technology

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Kuvaus

The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

Pituus : 317

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Otsikot

H1	H2	H3	H4	H5	H6
1	270	0	0	0	0

[H1] Blog Posts
[H2] Device Clock Generation
[H2] Quiz #24: Is there an AXI bug here?
[H2] Comparing the Xilinx MIG with an open source DDR3 controller
[H2] Wrap addressing
[H2] Your problem is not AXI
[H2] My Personal Journey in Verification
[H2] Debugging video from across the ocean
[H2] Bringing up Kimos
[H2] Chasing resets
[H2] 2023, Year in review
[H2] An Overview of a 10Gb Ethernet Switch
[H2] SDIO RX: Bugs found w/ Formal methods
[H2] Using a Verilog task to simulate a packet generator for an SDIO controller
[H2] Introducing the ZipCPU v3.0
[H2] What is a Virtual Packet FIFO?
[H2] What is a SwiC?
[H2] Debugging the Hard Stuff
[H2] Your soft-core CPU won't boot. Where should you start debugging?
[H2] Thanksgiving! I have much to be thankful for
[H2] Quiz #23: Can this assertion fail?
[H2] A first lesson in sales pitches: Honesty
[H2] Quiz #22: Handling cover failures
[H2] Measuring the Steps to Design Checkoff
[H2] Assignment delay's and Verilog's wait statement
[H2] It's not my fault! Your code is broken.
[H2] Protocol Design for Network Debugging
[H2] Quiz #21: Verifying all configurations of a design
[H2] ZipCPU Lesson: If it's not tested, it doesn't work.
[H2] A Coming Economic Downturn? or Worse?
[H2] Quiz #20: Using $stable in a multiclock environment
[H2] Learning AXI: Where to start?
[H2] Bringing up a new piece of hardware -- what can go wrong?
[H2] Rethinking Video with AXI video streams
[H2] AXI Stream is broken
[H2] 2020 and 2021 in review
[H2] Quiz #19: Using disable iff in a concurrent assertion
[H2] Creating a Simple AXI-Lite Master for the Hexbus
[H2] Envisioning the Ultimate I2C Controller
[H2] Clock Gating
[H2] Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
[H2] Quiz #18: Failures in clocked immediate assertions
[H2] AXI Handshaking Rules
[H2] Measuring AXI latency and throughput performance
[H2] Quiz #17: Induction failures
[H2] The other half of the Gospel
[H2] CPU based simulation, first thoughts
[H2] Quiz #16: Immediate assertions in the presence of asynchronous resets
[H2] Building a Better Verilog Multiply for the ZipCPU
[H2] Examples of AXI4 bus masters
[H2] Quiz #15: Pass-through memory
[H2] Fixing Xilinx's Broken AXI-lite Design in VHDL
[H2] Building a Simple AXI-lite Memory Controller
[H2] Common AXI Themes on Xilinx's Forum
[H2] Whatever happened to the ZipOS?
[H2] Lessons learned while building an ASIC design
[H2] The FPGA designer who didn't get the job
[H2] Ultimate Logic
[H2] Quiz #14: Two nearly identical frequencies
[H2] Formally verifying register handling
[H2] Is it possible to make a living as a solo digital design engineer?
[H2] Spectrograms need Window Functions
[H2] A fun Friday evening--verifying an AXI-lite slave
[H2] Moving values and strobes cross clock domains
[H2] Quiz #13: Temporal assertion equivalences
[H2] Run length encoding an AXI stream
[H2] Driving an output on both edges of the clock
[H2] Building a Downsampling Filter
[H2] I have a brand new piece of IP. How shall I verify it?
[H2] Measuring clock speed
[H2] The hard part of building a bursting AXI Master
[H2] Four keys to getting your design to work the first time
[H2] Quiz #12: Catching extraneous acknowledgments
[H2] Building a Protocol Firewall
[H2] Debugging AXI Streams
[H2] Adding an AXI-Lite interface to your Verilator test script
[H2] Re: What does your design flow look like?
[H2] Building a basic AXI Master
[H2] Cheap Spectral Estimation
[H2] Locally resetting an AXI component
[H2] Adjusting our logic PLL to handle I&Q
[H2] Buidilng an AXI-Lite slave the easy way
[H2] The Faith of a Mustard Seed
[H2] A Histogram Gone Bad
[H2] Quiz #11: Induction and clock enables
[H2] Quiz #10: Checking stall conditions
[H2] Lessons in Hardware Reuse
[H2] 2019: AXI Meets Formal Verification
[H2] The Christmas Gospel
[H2] Using a Histogram to Debug A/D Data Streams
[H2] Quiz #9: Immediate assertions midst blocking assignments
[H2] Quiz #8: Will this pass a bounded model check?
[H2] The ZipCPU meets blinky
[H2] Formally Verifying a General Purpose Ultra-Micro Controller
[H2] Quiz #7: Returning to $past() and our counter again
[H2] Putting the pieces together to build a data recorder
[H2] Is formal verfication enough, or is simulation required?
[H2] Quiz #6: Synchronous logic in Asynchronous contexts
[H2] AXI Verification, the story so far
[H2] Understanding AutoFPGA's address assignment algorithm
[H2] Quiz #5: Immediate vs Concurrent Assertions
[H2] Connecting lots of slaves to a bus without using a lot of logic
[H2] Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
[H2] Technology Debt and AutoFPGA, the bill just came due
[H2] Xilinx deleted this post
[H2] Quiz #3: Will formal verification prove this counter keeps its bounds?
[H2] Planning an Intermediate Design Tutorial
[H2] Quiz #2: Will this counter pass formal verification?
[H2] Quiz #1: Will the assertion below ever fail?
[H2] Just how long does a formal proof take to finish?
[H2] Lessons learned while building crossbar interconnects
[H2] Breaking all the rules to create an arbitrary clock signal
[H2] Building the perfect AXI4 slave
[H2] Building a Skid Buffer for AXI processing
[H2] Examining Xilinx's AXI demonstration core
[H2] Understanding AXI Addressing
[H2] Project Ideas: PMod AMP2
[H2] Applying Formal Methods to the Events of the Resurrection
[H2] The most common AXI mistake
[H2] The ZipCPU's Interrupt Controller
[H2] Logic usage and decoding return results with cascaded multiplexers
[H2] Building a universal QSPI flash controller
[H2] Introducing the ArrowZip ZipCPU design, featuring the Max-1000
[H2] Using Sequence Properties to Verify a Serial Port Transmitter
[H2] Why does blinky make a CPU appear to be so slow?
[H2] Debugging a CPU
[H2] Building a custom yet functional AXI-lite slave
[H2] ZipCPU highlights from 2018
[H2] Using a formal property file to verify an AXI-lite peripheral
[H2] AutoFPGA's linker script support gets an update
[H2] Makefiles for formal proofs with SymbiYosys
[H2] Swapping assumptions and assertions doesn't work
[H2] Building a video controller: it's just a pair of counters
[H2] Accessing the registers of a SoC+FPGA
[H2] Taking a look at the TinyFPGA BX
[H2] To my new readers and my new twitter followers, welcome!
[H2] An Open Source Pipelined FFT Generator
[H2] It's time for ORCONF 2018!
[H2] My design works in simulation, but not in hardware. Can formal methods help me?
[H2] Handling multiple clocks with Verilator
[H2] RE: Building a simulation for my design? What does that mean?
[H2] How to build a SPI Flash Controller for an FPGA
[H2] Reasons why Synthesis might not match Simulation
[H2] Why I like Formal: the ZipCPU and the ICO board
[H2] What does Formal Development look like in Practice?
[H2] Formally Verifying Memory and Cache Components
[H2] Crossing clock domains with an Asynchronous FIFO
[H2] Formally Verifying Asynchronous Components
[H2] A Slow but Symmetric FIR Filter Implementation
[H2] Updated Projects List
[H2] Aggregating verified modules together
[H2] ZipTimer: A simple countdown timer
[H2] Formally Verifying an Asynchronous Reset
[H2] What would you like to see on the ZipCPU blog?
[H2] Will formal methods ever find a bug in a working CPU?
[H2] Resurrection Day!
[H2] Quadratic fits are entirely inappropriate for DSP
[H2] Pipelining a Prefetch
[H2] Is formal really all that hard?
[H2] An Exercise in using Formal Induction
[H2] Want to use ZBasic? Let's have some fun--no actual FPGA required!
[H2] Debugging a Cyclone-V
[H2] ZipCPU toolchain and initial test
[H2] Updating ZipCPU files
[H2] Interpolation is just a special type of convolution
[H2] A Quick Introduction to the ZipCPU Instruction Set
[H2] Top 10 ZipCPU blog posts for 2017
[H2] A better filter implementation for slower signals
[H2] Mystery post: The ugliest bug I've ever encountered
[H2] Arrow's Max-1000: A gem for all the wrong reasons
[H2] Building a Simple Logic PLL
[H2] Building a Numerically Controlled Oscillator
[H2] Testing the fast, generic FIR filter
[H2] Thank you!
[H2] Measuring the frequency response of a filter under test
[H2] Building a prefetch module for the ZipCPU
[H2] Generating more than one bit at a time with an LFSR
[H2] An example LFSR
[H2] A Configurable Signal Delay Element
[H2] Building Formal Assumptions to Describe Wishbone Behaviour
[H2] The Interface to a Generic Filtering Testbench
[H2] Good Software Engineering Principles Apply to Students Too
[H2] Generating Pseudo-Random Numbers on an FPGA
[H2] Some Simple Clock-Domain Crossing Solutions
[H2] My first experience with Formal Methods
[H2] Just some notes to new readers of the ZipCPU blog
[H2] Implementing the Moving Average (Boxcar) filter
[H2] FPGAs vs ASICs
[H2] It's all about the interfaces
[H2] Using AutoFPGA to connect simple registers to a debugging bus
[H2] A Brief Introduction to AutoFPGA
[H2] A CORDIC testbench
[H2] A Cheaper Fast FIR Filter
[H2] Understanding the effects of Quantization
[H2] Clocks for Software Engineers
[H2] Demonstrating the improved PWM waveform
[H2] Building a high speed Finite Impulse Response (FIR) Digital Filter
[H2] Even I get stuck in FPGA Hell
[H2] Glad I went to ORCONF
[H2] Off to ORCONF-2017!
[H2] Reinventing PWM
[H2] Big Money Engineering Integrity
[H2] CORDIC part two: rectangular to polar conversion
[H2] Using a CORDIC to calculate sines and cosines in an FPGA
[H2] Building a quarter sine-wave lookup table
[H2] Debugging your soft-core CPU within an FPGA
[H2] The ZipCPU's pipeline logic
[H2] Rules for new FPGA designers
[H2] Two of the Simplest Digital filters
[H2] Strategies for pipelining logic
[H2] What would cause you to lie?
[H2] A Simple ALU, drawn from the ZipCPU
[H2] Series: Debouncing in Digital Logic
[H2] Using a debug-bus to Measure Bouncing
[H2] Measuring Contact Bounce
[H2] How to eliminate button bounces with digital logic
[H2] Visualizing Contact Bounce
[H2] ZipCPU Advertising
[H2] Writing your own VCD File
[H2] Linear Interpolation
[H2] Getting the basic FIFO right
[H2] Windows FPGA designers may not need a Linux machine ... yet
[H2] How to build a simulation based debugger for your own soft-core CPU
[H2] How to Debug a DSP algorithm
[H2] Rounding Numbers without Adding a Bias
[H2] Bit growth in FPGA arithmetic
[H2] A Basic Upsampling Linear Interpolator
[H2] Verilator doesn't find everything (today)
[H2] Design Needs when Debugging a SoftCore CPU
[H2] The simplest sine wave generator within an FPGA
[H2] Getting Started with the Wishbone Scope
[H2] Finishing off the debugging bus: building a software interface
[H2] Why you want a debug port into your FPGA
[H2] Simulating an FPGA through the debugging interface
[H2] My own FPGA debugging philosophy
[H2] Building a very simple wishbone interconnect
[H2] Taking a New Look at Verilator
[H2] Putting our Debugging Bus RTL Components Together
[H2] Sending bus idle notifications down the line
[H2] Why Use a Network Interface to your FPGA
[H2] Support me on Patreon
[H2] The debugging bus: a goal for FPGA interaction
[H2] Adding interrupt reporting to our debugging bus
[H2] How to send our bus results back out the serial port
[H2] No PI for you
[H2] How to create bus command words, from a 7-bit data stream
[H2] Minimizing FPGA Resource Utilization
[H2] A College Student's Response to the FPGA Design Process
[H2] Building a Simple Wishbone Master
[H2] Building A Simple In-Circuit Logic Analyzer
[H2] Nearest Neighbor Interpolation
[H2] An Overview of a Wishbone-UART Bridge
[H2] Campus Sidewalks and FPGA Design
[H2] Controlling Timing within an FPGA
[H2] The Actual FPGA Design Process
[H2] Building a simple wishbone slave
[H2] Bus Select Lines
[H2] FFT debugging
[H2] Debugging an FPGA through the serial port--first steps
[H2] That first serial port: Debugging when you are blind
[H2] Building a simple bus
[H2] Moving to memory
[H2] A Vision for Controlling FPGA Logic
[H2] Which comes first: the CPU or the peripherals?
[H2] Knight Rider
[H2] FPGA Hell
[H2] Blinky
[H2] Most common Digilent FPGA support requests
[H2] Cannot be done
[H2] Welcome to the ZipCPU blog!
[H2] The ZipCPU by Gisselquist Technology

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Ankkuri	Tyyppi	Mehu
About Us	Sisäinen	Antaa mehua
FPGA Hell	Sisäinen	Antaa mehua
Tutorial	Sisäinen	Antaa mehua
Formal training	Sisäinen	Antaa mehua
Quizzes	Sisäinen	Antaa mehua
Projects	Sisäinen	Antaa mehua
Site Index	Sisäinen	Antaa mehua
Device Clock Generation	Sisäinen	Antaa mehua
Quiz #24: Is there an AXI bug here?	Sisäinen	Antaa mehua
Comparing the Xilinx MIG with an open source DDR3 controller	Sisäinen	Antaa mehua
Wrap addressing	Sisäinen	Antaa mehua
Your problem is not AXI	Sisäinen	Antaa mehua
My Personal Journey in Verification	Sisäinen	Antaa mehua
Debugging video from across the ocean	Sisäinen	Antaa mehua
Bringing up Kimos	Sisäinen	Antaa mehua
Chasing resets	Sisäinen	Antaa mehua
2023, Year in review	Sisäinen	Antaa mehua
An Overview of a 10Gb Ethernet Switch	Sisäinen	Antaa mehua
SDIO RX: Bugs found w/ Formal methods	Sisäinen	Antaa mehua
Using a Verilog task to simulate a packet generator for an SDIO controller	Sisäinen	Antaa mehua
Introducing the ZipCPU v3.0	Sisäinen	Antaa mehua
What is a Virtual Packet FIFO?	Sisäinen	Antaa mehua
What is a SwiC?	Sisäinen	Antaa mehua
Debugging the Hard Stuff	Sisäinen	Antaa mehua
Your soft-core CPU won't boot. Where should you start debugging?	Sisäinen	Antaa mehua
Thanksgiving! I have much to be thankful for	Sisäinen	Antaa mehua
Quiz #23: Can this assertion fail?	Sisäinen	Antaa mehua
A first lesson in sales pitches: Honesty	Sisäinen	Antaa mehua
Quiz #22: Handling cover failures	Sisäinen	Antaa mehua
Measuring the Steps to Design Checkoff	Sisäinen	Antaa mehua
Assignment delay's and Verilog's wait statement	Sisäinen	Antaa mehua
It's not my fault! Your code is broken.	Sisäinen	Antaa mehua
Protocol Design for Network Debugging	Sisäinen	Antaa mehua
Quiz #21: Verifying all configurations of a design	Sisäinen	Antaa mehua
ZipCPU Lesson: If it's not tested, it doesn't work.	Sisäinen	Antaa mehua
A Coming Economic Downturn? or Worse?	Sisäinen	Antaa mehua
Quiz #20: Using $stable in a multiclock environment	Sisäinen	Antaa mehua
Learning AXI: Where to start?	Sisäinen	Antaa mehua
Bringing up a new piece of hardware -- what can go wrong?	Sisäinen	Antaa mehua
Rethinking Video with AXI video streams	Sisäinen	Antaa mehua
AXI Stream is broken	Sisäinen	Antaa mehua
2020 and 2021 in review	Sisäinen	Antaa mehua
Quiz #19: Using disable iff in a concurrent assertion	Sisäinen	Antaa mehua
Creating a Simple AXI-Lite Master for the Hexbus	Sisäinen	Antaa mehua
Envisioning the Ultimate I2C Controller	Sisäinen	Antaa mehua
Clock Gating	Sisäinen	Antaa mehua
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4	Sisäinen	Antaa mehua
Quiz #18: Failures in clocked immediate assertions	Sisäinen	Antaa mehua
AXI Handshaking Rules	Sisäinen	Antaa mehua
Measuring AXI latency and throughput performance	Sisäinen	Antaa mehua
Quiz #17: Induction failures	Sisäinen	Antaa mehua
The other half of the Gospel	Sisäinen	Antaa mehua
CPU based simulation, first thoughts	Sisäinen	Antaa mehua
Quiz #16: Immediate assertions in the presence of asynchronous resets	Sisäinen	Antaa mehua
Building a Better Verilog Multiply for the ZipCPU	Sisäinen	Antaa mehua
Examples of AXI4 bus masters	Sisäinen	Antaa mehua
Quiz #15: Pass-through memory	Sisäinen	Antaa mehua
Fixing Xilinx's Broken AXI-lite Design in VHDL	Sisäinen	Antaa mehua
Building a Simple AXI-lite Memory Controller	Sisäinen	Antaa mehua
Common AXI Themes on Xilinx's Forum	Sisäinen	Antaa mehua
Whatever happened to the ZipOS?	Sisäinen	Antaa mehua
Lessons learned while building an ASIC design	Sisäinen	Antaa mehua
The FPGA designer who didn't get the job	Sisäinen	Antaa mehua
Ultimate Logic	Sisäinen	Antaa mehua
Quiz #14: Two nearly identical frequencies	Sisäinen	Antaa mehua
Formally verifying register handling	Sisäinen	Antaa mehua
Is it possible to make a living as a solo digital design engineer?	Sisäinen	Antaa mehua
Spectrograms need Window Functions	Sisäinen	Antaa mehua
A fun Friday evening--verifying an AXI-lite slave	Sisäinen	Antaa mehua
Moving values and strobes cross clock domains	Sisäinen	Antaa mehua
Quiz #13: Temporal assertion equivalences	Sisäinen	Antaa mehua
Run length encoding an AXI stream	Sisäinen	Antaa mehua
Driving an output on both edges of the clock	Sisäinen	Antaa mehua
Building a Downsampling Filter	Sisäinen	Antaa mehua
I have a brand new piece of IP. How shall I verify it?	Sisäinen	Antaa mehua
Measuring clock speed	Sisäinen	Antaa mehua
The hard part of building a bursting AXI Master	Sisäinen	Antaa mehua
Four keys to getting your design to work the first time	Sisäinen	Antaa mehua
Quiz #12: Catching extraneous acknowledgments	Sisäinen	Antaa mehua
Building a Protocol Firewall	Sisäinen	Antaa mehua
Debugging AXI Streams	Sisäinen	Antaa mehua
Adding an AXI-Lite interface to your Verilator test script	Sisäinen	Antaa mehua
Re: What does your design flow look like?	Sisäinen	Antaa mehua
Building a basic AXI Master	Sisäinen	Antaa mehua
Cheap Spectral Estimation	Sisäinen	Antaa mehua
Locally resetting an AXI component	Sisäinen	Antaa mehua
Adjusting our logic PLL to handle I&Q	Sisäinen	Antaa mehua
Buidilng an AXI-Lite slave the easy way	Sisäinen	Antaa mehua
The Faith of a Mustard Seed	Sisäinen	Antaa mehua
A Histogram Gone Bad	Sisäinen	Antaa mehua
Quiz #11: Induction and clock enables	Sisäinen	Antaa mehua
Quiz #10: Checking stall conditions	Sisäinen	Antaa mehua
Lessons in Hardware Reuse	Sisäinen	Antaa mehua
2019: AXI Meets Formal Verification	Sisäinen	Antaa mehua
The Christmas Gospel	Sisäinen	Antaa mehua
Using a Histogram to Debug A/D Data Streams	Sisäinen	Antaa mehua
Quiz #9: Immediate assertions midst blocking assignments	Sisäinen	Antaa mehua
Quiz #8: Will this pass a bounded model check?	Sisäinen	Antaa mehua
The ZipCPU meets blinky	Sisäinen	Antaa mehua
Formally Verifying a General Purpose Ultra-Micro Controller	Sisäinen	Antaa mehua
Quiz #7: Returning to $past() and our counter again	Sisäinen	Antaa mehua
Putting the pieces together to build a data recorder	Sisäinen	Antaa mehua
Is formal verfication enough, or is simulation required?	Sisäinen	Antaa mehua
Quiz #6: Synchronous logic in Asynchronous contexts	Sisäinen	Antaa mehua
AXI Verification, the story so far	Sisäinen	Antaa mehua
Understanding AutoFPGA's address assignment algorithm	Sisäinen	Antaa mehua
Quiz #5: Immediate vs Concurrent Assertions	Sisäinen	Antaa mehua
Connecting lots of slaves to a bus without using a lot of logic	Sisäinen	Antaa mehua
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?	Sisäinen	Antaa mehua
Technology Debt and AutoFPGA, the bill just came due	Sisäinen	Antaa mehua
Xilinx deleted this post	Sisäinen	Antaa mehua
Quiz #3: Will formal verification prove this counter keeps its bounds?	Sisäinen	Antaa mehua
Planning an Intermediate Design Tutorial	Sisäinen	Antaa mehua
Quiz #2: Will this counter pass formal verification?	Sisäinen	Antaa mehua
Quiz #1: Will the assertion below ever fail?	Sisäinen	Antaa mehua
Just how long does a formal proof take to finish?	Sisäinen	Antaa mehua
Lessons learned while building crossbar interconnects	Sisäinen	Antaa mehua
Breaking all the rules to create an arbitrary clock signal	Sisäinen	Antaa mehua
Building the perfect AXI4 slave	Sisäinen	Antaa mehua
Building a Skid Buffer for AXI processing	Sisäinen	Antaa mehua
Examining Xilinx's AXI demonstration core	Sisäinen	Antaa mehua
Understanding AXI Addressing	Sisäinen	Antaa mehua
Project Ideas: PMod AMP2	Sisäinen	Antaa mehua
Applying Formal Methods to the Events of the Resurrection	Sisäinen	Antaa mehua
The most common AXI mistake	Sisäinen	Antaa mehua
The ZipCPU's Interrupt Controller	Sisäinen	Antaa mehua
Logic usage and decoding return results with cascaded multiplexers	Sisäinen	Antaa mehua
Building a universal QSPI flash controller	Sisäinen	Antaa mehua
Introducing the ArrowZip ZipCPU design, featuring the Max-1000	Sisäinen	Antaa mehua
Using Sequence Properties to Verify a Serial Port Transmitter	Sisäinen	Antaa mehua
Why does blinky make a CPU appear to be so slow?	Sisäinen	Antaa mehua
Debugging a CPU	Sisäinen	Antaa mehua
Building a custom yet functional AXI-lite slave	Sisäinen	Antaa mehua
ZipCPU highlights from 2018	Sisäinen	Antaa mehua
Using a formal property file to verify an AXI-lite peripheral	Sisäinen	Antaa mehua
AutoFPGA's linker script support gets an update	Sisäinen	Antaa mehua
Makefiles for formal proofs with SymbiYosys	Sisäinen	Antaa mehua
Swapping assumptions and assertions doesn't work	Sisäinen	Antaa mehua
Building a video controller: it's just a pair of counters	Sisäinen	Antaa mehua
Accessing the registers of a SoC+FPGA	Sisäinen	Antaa mehua
Taking a look at the TinyFPGA BX	Sisäinen	Antaa mehua
To my new readers and my new twitter followers, welcome!	Sisäinen	Antaa mehua
An Open Source Pipelined FFT Generator	Sisäinen	Antaa mehua
It's time for ORCONF 2018!	Sisäinen	Antaa mehua
My design works in simulation, but not in hardware. Can formal methods help me?	Sisäinen	Antaa mehua
Handling multiple clocks with Verilator	Sisäinen	Antaa mehua
RE: Building a simulation for my design? What does that mean?	Sisäinen	Antaa mehua
How to build a SPI Flash Controller for an FPGA	Sisäinen	Antaa mehua
Reasons why Synthesis might not match Simulation	Sisäinen	Antaa mehua
Why I like Formal: the ZipCPU and the ICO board	Sisäinen	Antaa mehua
What does Formal Development look like in Practice?	Sisäinen	Antaa mehua
Formally Verifying Memory and Cache Components	Sisäinen	Antaa mehua
Crossing clock domains with an Asynchronous FIFO	Sisäinen	Antaa mehua
Formally Verifying Asynchronous Components	Sisäinen	Antaa mehua
A Slow but Symmetric FIR Filter Implementation	Sisäinen	Antaa mehua
Updated Projects List	Sisäinen	Antaa mehua
Aggregating verified modules together	Sisäinen	Antaa mehua
ZipTimer: A simple countdown timer	Sisäinen	Antaa mehua
Formally Verifying an Asynchronous Reset	Sisäinen	Antaa mehua
What would you like to see on the ZipCPU blog?	Sisäinen	Antaa mehua
Will formal methods ever find a bug in a working CPU?	Sisäinen	Antaa mehua
Resurrection Day!	Sisäinen	Antaa mehua
Quadratic fits are entirely inappropriate for DSP	Sisäinen	Antaa mehua
Pipelining a Prefetch	Sisäinen	Antaa mehua
Is formal really all that hard?	Sisäinen	Antaa mehua
An Exercise in using Formal Induction	Sisäinen	Antaa mehua
Want to use ZBasic? Let's have some fun--no actual FPGA required!	Sisäinen	Antaa mehua
Debugging a Cyclone-V	Sisäinen	Antaa mehua
ZipCPU toolchain and initial test	Sisäinen	Antaa mehua
Updating ZipCPU files	Sisäinen	Antaa mehua
Interpolation is just a special type of convolution	Sisäinen	Antaa mehua
A Quick Introduction to the ZipCPU Instruction Set	Sisäinen	Antaa mehua
Top 10 ZipCPU blog posts for 2017	Sisäinen	Antaa mehua
A better filter implementation for slower signals	Sisäinen	Antaa mehua
Mystery post: The ugliest bug I've ever encountered	Sisäinen	Antaa mehua
Arrow's Max-1000: A gem for all the wrong reasons	Sisäinen	Antaa mehua
Building a Simple Logic PLL	Sisäinen	Antaa mehua
Building a Numerically Controlled Oscillator	Sisäinen	Antaa mehua
Testing the fast, generic FIR filter	Sisäinen	Antaa mehua
Thank you!	Sisäinen	Antaa mehua
Measuring the frequency response of a filter under test	Sisäinen	Antaa mehua
Building a prefetch module for the ZipCPU	Sisäinen	Antaa mehua
Generating more than one bit at a time with an LFSR	Sisäinen	Antaa mehua
An example LFSR	Sisäinen	Antaa mehua
A Configurable Signal Delay Element	Sisäinen	Antaa mehua
Building Formal Assumptions to Describe Wishbone Behaviour	Sisäinen	Antaa mehua
The Interface to a Generic Filtering Testbench	Sisäinen	Antaa mehua
Good Software Engineering Principles Apply to Students Too	Sisäinen	Antaa mehua
Generating Pseudo-Random Numbers on an FPGA	Sisäinen	Antaa mehua
Some Simple Clock-Domain Crossing Solutions	Sisäinen	Antaa mehua
My first experience with Formal Methods	Sisäinen	Antaa mehua
Just some notes to new readers of the ZipCPU blog	Sisäinen	Antaa mehua
Implementing the Moving Average (Boxcar) filter	Sisäinen	Antaa mehua
FPGAs vs ASICs	Sisäinen	Antaa mehua
It's all about the interfaces	Sisäinen	Antaa mehua
Using AutoFPGA to connect simple registers to a debugging bus	Sisäinen	Antaa mehua
A Brief Introduction to AutoFPGA	Sisäinen	Antaa mehua
A CORDIC testbench	Sisäinen	Antaa mehua
A Cheaper Fast FIR Filter	Sisäinen	Antaa mehua
Understanding the effects of Quantization	Sisäinen	Antaa mehua
Clocks for Software Engineers	Sisäinen	Antaa mehua
Demonstrating the improved PWM waveform	Sisäinen	Antaa mehua
Building a high speed Finite Impulse Response (FIR) Digital Filter	Sisäinen	Antaa mehua
Even I get stuck in FPGA Hell	Sisäinen	Antaa mehua
Glad I went to ORCONF	Sisäinen	Antaa mehua
Off to ORCONF-2017!	Sisäinen	Antaa mehua
Reinventing PWM	Sisäinen	Antaa mehua
Big Money Engineering Integrity	Sisäinen	Antaa mehua
CORDIC part two: rectangular to polar conversion	Sisäinen	Antaa mehua
Using a CORDIC to calculate sines and cosines in an FPGA	Sisäinen	Antaa mehua
Building a quarter sine-wave lookup table	Sisäinen	Antaa mehua
Debugging your soft-core CPU within an FPGA	Sisäinen	Antaa mehua
The ZipCPU's pipeline logic	Sisäinen	Antaa mehua
Rules for new FPGA designers	Sisäinen	Antaa mehua
Two of the Simplest Digital filters	Sisäinen	Antaa mehua
Strategies for pipelining logic	Sisäinen	Antaa mehua
What would cause you to lie?	Sisäinen	Antaa mehua
A Simple ALU, drawn from the ZipCPU	Sisäinen	Antaa mehua
Series: Debouncing in Digital Logic	Sisäinen	Antaa mehua
Using a debug-bus to Measure Bouncing	Sisäinen	Antaa mehua
Measuring Contact Bounce	Sisäinen	Antaa mehua
How to eliminate button bounces with digital logic	Sisäinen	Antaa mehua
Visualizing Contact Bounce	Sisäinen	Antaa mehua
ZipCPU Advertising	Sisäinen	Antaa mehua
Writing your own VCD File	Sisäinen	Antaa mehua
Linear Interpolation	Sisäinen	Antaa mehua
Getting the basic FIFO right	Sisäinen	Antaa mehua
Windows FPGA designers may not need a Linux machine ... yet	Sisäinen	Antaa mehua
How to build a simulation based debugger for your own soft-core CPU	Sisäinen	Antaa mehua
How to Debug a DSP algorithm	Sisäinen	Antaa mehua
Rounding Numbers without Adding a Bias	Sisäinen	Antaa mehua
Bit growth in FPGA arithmetic	Sisäinen	Antaa mehua
A Basic Upsampling Linear Interpolator	Sisäinen	Antaa mehua
Verilator doesn't find everything (today)	Sisäinen	Antaa mehua
Design Needs when Debugging a SoftCore CPU	Sisäinen	Antaa mehua
The simplest sine wave generator within an FPGA	Sisäinen	Antaa mehua
Getting Started with the Wishbone Scope	Sisäinen	Antaa mehua
Finishing off the debugging bus: building a software interface	Sisäinen	Antaa mehua
Why you want a debug port into your FPGA	Sisäinen	Antaa mehua
Simulating an FPGA through the debugging interface	Sisäinen	Antaa mehua
My own FPGA debugging philosophy	Sisäinen	Antaa mehua
Building a very simple wishbone interconnect	Sisäinen	Antaa mehua
Taking a New Look at Verilator	Sisäinen	Antaa mehua
Putting our Debugging Bus RTL Components Together	Sisäinen	Antaa mehua
Sending bus idle notifications down the line	Sisäinen	Antaa mehua
Why Use a Network Interface to your FPGA	Sisäinen	Antaa mehua
Support me on Patreon	Sisäinen	Antaa mehua
The debugging bus: a goal for FPGA interaction	Sisäinen	Antaa mehua
Adding interrupt reporting to our debugging bus	Sisäinen	Antaa mehua
How to send our bus results back out the serial port	Sisäinen	Antaa mehua
No PI for you	Sisäinen	Antaa mehua
How to create bus command words, from a 7-bit data stream	Sisäinen	Antaa mehua
Minimizing FPGA Resource Utilization	Sisäinen	Antaa mehua
A College Student's Response to the FPGA Design Process	Sisäinen	Antaa mehua
Building a Simple Wishbone Master	Sisäinen	Antaa mehua
Building A Simple In-Circuit Logic Analyzer	Sisäinen	Antaa mehua
Nearest Neighbor Interpolation	Sisäinen	Antaa mehua
An Overview of a Wishbone-UART Bridge	Sisäinen	Antaa mehua
Campus Sidewalks and FPGA Design	Sisäinen	Antaa mehua
Controlling Timing within an FPGA	Sisäinen	Antaa mehua
The Actual FPGA Design Process	Sisäinen	Antaa mehua
Building a simple wishbone slave	Sisäinen	Antaa mehua
Bus Select Lines	Sisäinen	Antaa mehua
FFT debugging	Sisäinen	Antaa mehua
Debugging an FPGA through the serial port--first steps	Sisäinen	Antaa mehua
That first serial port: Debugging when you are blind	Sisäinen	Antaa mehua
Building a simple bus	Sisäinen	Antaa mehua
Moving to memory	Sisäinen	Antaa mehua
A Vision for Controlling FPGA Logic	Sisäinen	Antaa mehua
Which comes first: the CPU or the peripherals?	Sisäinen	Antaa mehua
Knight Rider	Sisäinen	Antaa mehua
FPGA Hell	Sisäinen	Antaa mehua
Blinky	Sisäinen	Antaa mehua
Most common Digilent FPGA support requests	Sisäinen	Antaa mehua
Cannot be done	Sisäinen	Antaa mehua
Welcome to the ZipCPU blog!	Sisäinen	Antaa mehua
via RSS	Sisäinen	Antaa mehua

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