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The ZipCPU by Gisselquist Technology

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The ZipCPU by Gisselquist Technology

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The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

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Niveaux de titre

H1	H2	H3	H4	H5	H6
1	270	0	0	0	0

[H1] Blog Posts
[H2] Device Clock Generation
[H2] Quiz #24: Is there an AXI bug here?
[H2] Comparing the Xilinx MIG with an open source DDR3 controller
[H2] Wrap addressing
[H2] Your problem is not AXI
[H2] My Personal Journey in Verification
[H2] Debugging video from across the ocean
[H2] Bringing up Kimos
[H2] Chasing resets
[H2] 2023, Year in review
[H2] An Overview of a 10Gb Ethernet Switch
[H2] SDIO RX: Bugs found w/ Formal methods
[H2] Using a Verilog task to simulate a packet generator for an SDIO controller
[H2] Introducing the ZipCPU v3.0
[H2] What is a Virtual Packet FIFO?
[H2] What is a SwiC?
[H2] Debugging the Hard Stuff
[H2] Your soft-core CPU won't boot. Where should you start debugging?
[H2] Thanksgiving! I have much to be thankful for
[H2] Quiz #23: Can this assertion fail?
[H2] A first lesson in sales pitches: Honesty
[H2] Quiz #22: Handling cover failures
[H2] Measuring the Steps to Design Checkoff
[H2] Assignment delay's and Verilog's wait statement
[H2] It's not my fault! Your code is broken.
[H2] Protocol Design for Network Debugging
[H2] Quiz #21: Verifying all configurations of a design
[H2] ZipCPU Lesson: If it's not tested, it doesn't work.
[H2] A Coming Economic Downturn? or Worse?
[H2] Quiz #20: Using $stable in a multiclock environment
[H2] Learning AXI: Where to start?
[H2] Bringing up a new piece of hardware -- what can go wrong?
[H2] Rethinking Video with AXI video streams
[H2] AXI Stream is broken
[H2] 2020 and 2021 in review
[H2] Quiz #19: Using disable iff in a concurrent assertion
[H2] Creating a Simple AXI-Lite Master for the Hexbus
[H2] Envisioning the Ultimate I2C Controller
[H2] Clock Gating
[H2] Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
[H2] Quiz #18: Failures in clocked immediate assertions
[H2] AXI Handshaking Rules
[H2] Measuring AXI latency and throughput performance
[H2] Quiz #17: Induction failures
[H2] The other half of the Gospel
[H2] CPU based simulation, first thoughts
[H2] Quiz #16: Immediate assertions in the presence of asynchronous resets
[H2] Building a Better Verilog Multiply for the ZipCPU
[H2] Examples of AXI4 bus masters
[H2] Quiz #15: Pass-through memory
[H2] Fixing Xilinx's Broken AXI-lite Design in VHDL
[H2] Building a Simple AXI-lite Memory Controller
[H2] Common AXI Themes on Xilinx's Forum
[H2] Whatever happened to the ZipOS?
[H2] Lessons learned while building an ASIC design
[H2] The FPGA designer who didn't get the job
[H2] Ultimate Logic
[H2] Quiz #14: Two nearly identical frequencies
[H2] Formally verifying register handling
[H2] Is it possible to make a living as a solo digital design engineer?
[H2] Spectrograms need Window Functions
[H2] A fun Friday evening--verifying an AXI-lite slave
[H2] Moving values and strobes cross clock domains
[H2] Quiz #13: Temporal assertion equivalences
[H2] Run length encoding an AXI stream
[H2] Driving an output on both edges of the clock
[H2] Building a Downsampling Filter
[H2] I have a brand new piece of IP. How shall I verify it?
[H2] Measuring clock speed
[H2] The hard part of building a bursting AXI Master
[H2] Four keys to getting your design to work the first time
[H2] Quiz #12: Catching extraneous acknowledgments
[H2] Building a Protocol Firewall
[H2] Debugging AXI Streams
[H2] Adding an AXI-Lite interface to your Verilator test script
[H2] Re: What does your design flow look like?
[H2] Building a basic AXI Master
[H2] Cheap Spectral Estimation
[H2] Locally resetting an AXI component
[H2] Adjusting our logic PLL to handle I&Q
[H2] Buidilng an AXI-Lite slave the easy way
[H2] The Faith of a Mustard Seed
[H2] A Histogram Gone Bad
[H2] Quiz #11: Induction and clock enables
[H2] Quiz #10: Checking stall conditions
[H2] Lessons in Hardware Reuse
[H2] 2019: AXI Meets Formal Verification
[H2] The Christmas Gospel
[H2] Using a Histogram to Debug A/D Data Streams
[H2] Quiz #9: Immediate assertions midst blocking assignments
[H2] Quiz #8: Will this pass a bounded model check?
[H2] The ZipCPU meets blinky
[H2] Formally Verifying a General Purpose Ultra-Micro Controller
[H2] Quiz #7: Returning to $past() and our counter again
[H2] Putting the pieces together to build a data recorder
[H2] Is formal verfication enough, or is simulation required?
[H2] Quiz #6: Synchronous logic in Asynchronous contexts
[H2] AXI Verification, the story so far
[H2] Understanding AutoFPGA's address assignment algorithm
[H2] Quiz #5: Immediate vs Concurrent Assertions
[H2] Connecting lots of slaves to a bus without using a lot of logic
[H2] Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
[H2] Technology Debt and AutoFPGA, the bill just came due
[H2] Xilinx deleted this post
[H2] Quiz #3: Will formal verification prove this counter keeps its bounds?
[H2] Planning an Intermediate Design Tutorial
[H2] Quiz #2: Will this counter pass formal verification?
[H2] Quiz #1: Will the assertion below ever fail?
[H2] Just how long does a formal proof take to finish?
[H2] Lessons learned while building crossbar interconnects
[H2] Breaking all the rules to create an arbitrary clock signal
[H2] Building the perfect AXI4 slave
[H2] Building a Skid Buffer for AXI processing
[H2] Examining Xilinx's AXI demonstration core
[H2] Understanding AXI Addressing
[H2] Project Ideas: PMod AMP2
[H2] Applying Formal Methods to the Events of the Resurrection
[H2] The most common AXI mistake
[H2] The ZipCPU's Interrupt Controller
[H2] Logic usage and decoding return results with cascaded multiplexers
[H2] Building a universal QSPI flash controller
[H2] Introducing the ArrowZip ZipCPU design, featuring the Max-1000
[H2] Using Sequence Properties to Verify a Serial Port Transmitter
[H2] Why does blinky make a CPU appear to be so slow?
[H2] Debugging a CPU
[H2] Building a custom yet functional AXI-lite slave
[H2] ZipCPU highlights from 2018
[H2] Using a formal property file to verify an AXI-lite peripheral
[H2] AutoFPGA's linker script support gets an update
[H2] Makefiles for formal proofs with SymbiYosys
[H2] Swapping assumptions and assertions doesn't work
[H2] Building a video controller: it's just a pair of counters
[H2] Accessing the registers of a SoC+FPGA
[H2] Taking a look at the TinyFPGA BX
[H2] To my new readers and my new twitter followers, welcome!
[H2] An Open Source Pipelined FFT Generator
[H2] It's time for ORCONF 2018!
[H2] My design works in simulation, but not in hardware. Can formal methods help me?
[H2] Handling multiple clocks with Verilator
[H2] RE: Building a simulation for my design? What does that mean?
[H2] How to build a SPI Flash Controller for an FPGA
[H2] Reasons why Synthesis might not match Simulation
[H2] Why I like Formal: the ZipCPU and the ICO board
[H2] What does Formal Development look like in Practice?
[H2] Formally Verifying Memory and Cache Components
[H2] Crossing clock domains with an Asynchronous FIFO
[H2] Formally Verifying Asynchronous Components
[H2] A Slow but Symmetric FIR Filter Implementation
[H2] Updated Projects List
[H2] Aggregating verified modules together
[H2] ZipTimer: A simple countdown timer
[H2] Formally Verifying an Asynchronous Reset
[H2] What would you like to see on the ZipCPU blog?
[H2] Will formal methods ever find a bug in a working CPU?
[H2] Resurrection Day!
[H2] Quadratic fits are entirely inappropriate for DSP
[H2] Pipelining a Prefetch
[H2] Is formal really all that hard?
[H2] An Exercise in using Formal Induction
[H2] Want to use ZBasic? Let's have some fun--no actual FPGA required!
[H2] Debugging a Cyclone-V
[H2] ZipCPU toolchain and initial test
[H2] Updating ZipCPU files
[H2] Interpolation is just a special type of convolution
[H2] A Quick Introduction to the ZipCPU Instruction Set
[H2] Top 10 ZipCPU blog posts for 2017
[H2] A better filter implementation for slower signals
[H2] Mystery post: The ugliest bug I've ever encountered
[H2] Arrow's Max-1000: A gem for all the wrong reasons
[H2] Building a Simple Logic PLL
[H2] Building a Numerically Controlled Oscillator
[H2] Testing the fast, generic FIR filter
[H2] Thank you!
[H2] Measuring the frequency response of a filter under test
[H2] Building a prefetch module for the ZipCPU
[H2] Generating more than one bit at a time with an LFSR
[H2] An example LFSR
[H2] A Configurable Signal Delay Element
[H2] Building Formal Assumptions to Describe Wishbone Behaviour
[H2] The Interface to a Generic Filtering Testbench
[H2] Good Software Engineering Principles Apply to Students Too
[H2] Generating Pseudo-Random Numbers on an FPGA
[H2] Some Simple Clock-Domain Crossing Solutions
[H2] My first experience with Formal Methods
[H2] Just some notes to new readers of the ZipCPU blog
[H2] Implementing the Moving Average (Boxcar) filter
[H2] FPGAs vs ASICs
[H2] It's all about the interfaces
[H2] Using AutoFPGA to connect simple registers to a debugging bus
[H2] A Brief Introduction to AutoFPGA
[H2] A CORDIC testbench
[H2] A Cheaper Fast FIR Filter
[H2] Understanding the effects of Quantization
[H2] Clocks for Software Engineers
[H2] Demonstrating the improved PWM waveform
[H2] Building a high speed Finite Impulse Response (FIR) Digital Filter
[H2] Even I get stuck in FPGA Hell
[H2] Glad I went to ORCONF
[H2] Off to ORCONF-2017!
[H2] Reinventing PWM
[H2] Big Money Engineering Integrity
[H2] CORDIC part two: rectangular to polar conversion
[H2] Using a CORDIC to calculate sines and cosines in an FPGA
[H2] Building a quarter sine-wave lookup table
[H2] Debugging your soft-core CPU within an FPGA
[H2] The ZipCPU's pipeline logic
[H2] Rules for new FPGA designers
[H2] Two of the Simplest Digital filters
[H2] Strategies for pipelining logic
[H2] What would cause you to lie?
[H2] A Simple ALU, drawn from the ZipCPU
[H2] Series: Debouncing in Digital Logic
[H2] Using a debug-bus to Measure Bouncing
[H2] Measuring Contact Bounce
[H2] How to eliminate button bounces with digital logic
[H2] Visualizing Contact Bounce
[H2] ZipCPU Advertising
[H2] Writing your own VCD File
[H2] Linear Interpolation
[H2] Getting the basic FIFO right
[H2] Windows FPGA designers may not need a Linux machine ... yet
[H2] How to build a simulation based debugger for your own soft-core CPU
[H2] How to Debug a DSP algorithm
[H2] Rounding Numbers without Adding a Bias
[H2] Bit growth in FPGA arithmetic
[H2] A Basic Upsampling Linear Interpolator
[H2] Verilator doesn't find everything (today)
[H2] Design Needs when Debugging a SoftCore CPU
[H2] The simplest sine wave generator within an FPGA
[H2] Getting Started with the Wishbone Scope
[H2] Finishing off the debugging bus: building a software interface
[H2] Why you want a debug port into your FPGA
[H2] Simulating an FPGA through the debugging interface
[H2] My own FPGA debugging philosophy
[H2] Building a very simple wishbone interconnect
[H2] Taking a New Look at Verilator
[H2] Putting our Debugging Bus RTL Components Together
[H2] Sending bus idle notifications down the line
[H2] Why Use a Network Interface to your FPGA
[H2] Support me on Patreon
[H2] The debugging bus: a goal for FPGA interaction
[H2] Adding interrupt reporting to our debugging bus
[H2] How to send our bus results back out the serial port
[H2] No PI for you
[H2] How to create bus command words, from a 7-bit data stream
[H2] Minimizing FPGA Resource Utilization
[H2] A College Student's Response to the FPGA Design Process
[H2] Building a Simple Wishbone Master
[H2] Building A Simple In-Circuit Logic Analyzer
[H2] Nearest Neighbor Interpolation
[H2] An Overview of a Wishbone-UART Bridge
[H2] Campus Sidewalks and FPGA Design
[H2] Controlling Timing within an FPGA
[H2] The Actual FPGA Design Process
[H2] Building a simple wishbone slave
[H2] Bus Select Lines
[H2] FFT debugging
[H2] Debugging an FPGA through the serial port--first steps
[H2] That first serial port: Debugging when you are blind
[H2] Building a simple bus
[H2] Moving to memory
[H2] A Vision for Controlling FPGA Logic
[H2] Which comes first: the CPU or the peripherals?
[H2] Knight Rider
[H2] FPGA Hell
[H2] Blinky
[H2] Most common Digilent FPGA support requests
[H2] Cannot be done
[H2] Welcome to the ZipCPU blog!
[H2] The ZipCPU by Gisselquist Technology

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Texte d'ancre	Type	Juice
About Us	Interne	Passing Juice
FPGA Hell	Interne	Passing Juice
Tutorial	Interne	Passing Juice
Formal training	Interne	Passing Juice
Quizzes	Interne	Passing Juice
Projects	Interne	Passing Juice
Site Index	Interne	Passing Juice
Device Clock Generation	Interne	Passing Juice
Quiz #24: Is there an AXI bug here?	Interne	Passing Juice
Comparing the Xilinx MIG with an open source DDR3 controller	Interne	Passing Juice
Wrap addressing	Interne	Passing Juice
Your problem is not AXI	Interne	Passing Juice
My Personal Journey in Verification	Interne	Passing Juice
Debugging video from across the ocean	Interne	Passing Juice
Bringing up Kimos	Interne	Passing Juice
Chasing resets	Interne	Passing Juice
2023, Year in review	Interne	Passing Juice
An Overview of a 10Gb Ethernet Switch	Interne	Passing Juice
SDIO RX: Bugs found w/ Formal methods	Interne	Passing Juice
Using a Verilog task to simulate a packet generator for an SDIO controller	Interne	Passing Juice
Introducing the ZipCPU v3.0	Interne	Passing Juice
What is a Virtual Packet FIFO?	Interne	Passing Juice
What is a SwiC?	Interne	Passing Juice
Debugging the Hard Stuff	Interne	Passing Juice
Your soft-core CPU won't boot. Where should you start debugging?	Interne	Passing Juice
Thanksgiving! I have much to be thankful for	Interne	Passing Juice
Quiz #23: Can this assertion fail?	Interne	Passing Juice
A first lesson in sales pitches: Honesty	Interne	Passing Juice
Quiz #22: Handling cover failures	Interne	Passing Juice
Measuring the Steps to Design Checkoff	Interne	Passing Juice
Assignment delay's and Verilog's wait statement	Interne	Passing Juice
It's not my fault! Your code is broken.	Interne	Passing Juice
Protocol Design for Network Debugging	Interne	Passing Juice
Quiz #21: Verifying all configurations of a design	Interne	Passing Juice
ZipCPU Lesson: If it's not tested, it doesn't work.	Interne	Passing Juice
A Coming Economic Downturn? or Worse?	Interne	Passing Juice
Quiz #20: Using $stable in a multiclock environment	Interne	Passing Juice
Learning AXI: Where to start?	Interne	Passing Juice
Bringing up a new piece of hardware -- what can go wrong?	Interne	Passing Juice
Rethinking Video with AXI video streams	Interne	Passing Juice
AXI Stream is broken	Interne	Passing Juice
2020 and 2021 in review	Interne	Passing Juice
Quiz #19: Using disable iff in a concurrent assertion	Interne	Passing Juice
Creating a Simple AXI-Lite Master for the Hexbus	Interne	Passing Juice
Envisioning the Ultimate I2C Controller	Interne	Passing Juice
Clock Gating	Interne	Passing Juice
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4	Interne	Passing Juice
Quiz #18: Failures in clocked immediate assertions	Interne	Passing Juice
AXI Handshaking Rules	Interne	Passing Juice
Measuring AXI latency and throughput performance	Interne	Passing Juice
Quiz #17: Induction failures	Interne	Passing Juice
The other half of the Gospel	Interne	Passing Juice
CPU based simulation, first thoughts	Interne	Passing Juice
Quiz #16: Immediate assertions in the presence of asynchronous resets	Interne	Passing Juice
Building a Better Verilog Multiply for the ZipCPU	Interne	Passing Juice
Examples of AXI4 bus masters	Interne	Passing Juice
Quiz #15: Pass-through memory	Interne	Passing Juice
Fixing Xilinx's Broken AXI-lite Design in VHDL	Interne	Passing Juice
Building a Simple AXI-lite Memory Controller	Interne	Passing Juice
Common AXI Themes on Xilinx's Forum	Interne	Passing Juice
Whatever happened to the ZipOS?	Interne	Passing Juice
Lessons learned while building an ASIC design	Interne	Passing Juice
The FPGA designer who didn't get the job	Interne	Passing Juice
Ultimate Logic	Interne	Passing Juice
Quiz #14: Two nearly identical frequencies	Interne	Passing Juice
Formally verifying register handling	Interne	Passing Juice
Is it possible to make a living as a solo digital design engineer?	Interne	Passing Juice
Spectrograms need Window Functions	Interne	Passing Juice
A fun Friday evening--verifying an AXI-lite slave	Interne	Passing Juice
Moving values and strobes cross clock domains	Interne	Passing Juice
Quiz #13: Temporal assertion equivalences	Interne	Passing Juice
Run length encoding an AXI stream	Interne	Passing Juice
Driving an output on both edges of the clock	Interne	Passing Juice
Building a Downsampling Filter	Interne	Passing Juice
I have a brand new piece of IP. How shall I verify it?	Interne	Passing Juice
Measuring clock speed	Interne	Passing Juice
The hard part of building a bursting AXI Master	Interne	Passing Juice
Four keys to getting your design to work the first time	Interne	Passing Juice
Quiz #12: Catching extraneous acknowledgments	Interne	Passing Juice
Building a Protocol Firewall	Interne	Passing Juice
Debugging AXI Streams	Interne	Passing Juice
Adding an AXI-Lite interface to your Verilator test script	Interne	Passing Juice
Re: What does your design flow look like?	Interne	Passing Juice
Building a basic AXI Master	Interne	Passing Juice
Cheap Spectral Estimation	Interne	Passing Juice
Locally resetting an AXI component	Interne	Passing Juice
Adjusting our logic PLL to handle I&Q	Interne	Passing Juice
Buidilng an AXI-Lite slave the easy way	Interne	Passing Juice
The Faith of a Mustard Seed	Interne	Passing Juice
A Histogram Gone Bad	Interne	Passing Juice
Quiz #11: Induction and clock enables	Interne	Passing Juice
Quiz #10: Checking stall conditions	Interne	Passing Juice
Lessons in Hardware Reuse	Interne	Passing Juice
2019: AXI Meets Formal Verification	Interne	Passing Juice
The Christmas Gospel	Interne	Passing Juice
Using a Histogram to Debug A/D Data Streams	Interne	Passing Juice
Quiz #9: Immediate assertions midst blocking assignments	Interne	Passing Juice
Quiz #8: Will this pass a bounded model check?	Interne	Passing Juice
The ZipCPU meets blinky	Interne	Passing Juice
Formally Verifying a General Purpose Ultra-Micro Controller	Interne	Passing Juice
Quiz #7: Returning to $past() and our counter again	Interne	Passing Juice
Putting the pieces together to build a data recorder	Interne	Passing Juice
Is formal verfication enough, or is simulation required?	Interne	Passing Juice
Quiz #6: Synchronous logic in Asynchronous contexts	Interne	Passing Juice
AXI Verification, the story so far	Interne	Passing Juice
Understanding AutoFPGA's address assignment algorithm	Interne	Passing Juice
Quiz #5: Immediate vs Concurrent Assertions	Interne	Passing Juice
Connecting lots of slaves to a bus without using a lot of logic	Interne	Passing Juice
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?	Interne	Passing Juice
Technology Debt and AutoFPGA, the bill just came due	Interne	Passing Juice
Xilinx deleted this post	Interne	Passing Juice
Quiz #3: Will formal verification prove this counter keeps its bounds?	Interne	Passing Juice
Planning an Intermediate Design Tutorial	Interne	Passing Juice
Quiz #2: Will this counter pass formal verification?	Interne	Passing Juice
Quiz #1: Will the assertion below ever fail?	Interne	Passing Juice
Just how long does a formal proof take to finish?	Interne	Passing Juice
Lessons learned while building crossbar interconnects	Interne	Passing Juice
Breaking all the rules to create an arbitrary clock signal	Interne	Passing Juice
Building the perfect AXI4 slave	Interne	Passing Juice
Building a Skid Buffer for AXI processing	Interne	Passing Juice
Examining Xilinx's AXI demonstration core	Interne	Passing Juice
Understanding AXI Addressing	Interne	Passing Juice
Project Ideas: PMod AMP2	Interne	Passing Juice
Applying Formal Methods to the Events of the Resurrection	Interne	Passing Juice
The most common AXI mistake	Interne	Passing Juice
The ZipCPU's Interrupt Controller	Interne	Passing Juice
Logic usage and decoding return results with cascaded multiplexers	Interne	Passing Juice
Building a universal QSPI flash controller	Interne	Passing Juice
Introducing the ArrowZip ZipCPU design, featuring the Max-1000	Interne	Passing Juice
Using Sequence Properties to Verify a Serial Port Transmitter	Interne	Passing Juice
Why does blinky make a CPU appear to be so slow?	Interne	Passing Juice
Debugging a CPU	Interne	Passing Juice
Building a custom yet functional AXI-lite slave	Interne	Passing Juice
ZipCPU highlights from 2018	Interne	Passing Juice
Using a formal property file to verify an AXI-lite peripheral	Interne	Passing Juice
AutoFPGA's linker script support gets an update	Interne	Passing Juice
Makefiles for formal proofs with SymbiYosys	Interne	Passing Juice
Swapping assumptions and assertions doesn't work	Interne	Passing Juice
Building a video controller: it's just a pair of counters	Interne	Passing Juice
Accessing the registers of a SoC+FPGA	Interne	Passing Juice
Taking a look at the TinyFPGA BX	Interne	Passing Juice
To my new readers and my new twitter followers, welcome!	Interne	Passing Juice
An Open Source Pipelined FFT Generator	Interne	Passing Juice
It's time for ORCONF 2018!	Interne	Passing Juice
My design works in simulation, but not in hardware. Can formal methods help me?	Interne	Passing Juice
Handling multiple clocks with Verilator	Interne	Passing Juice
RE: Building a simulation for my design? What does that mean?	Interne	Passing Juice
How to build a SPI Flash Controller for an FPGA	Interne	Passing Juice
Reasons why Synthesis might not match Simulation	Interne	Passing Juice
Why I like Formal: the ZipCPU and the ICO board	Interne	Passing Juice
What does Formal Development look like in Practice?	Interne	Passing Juice
Formally Verifying Memory and Cache Components	Interne	Passing Juice
Crossing clock domains with an Asynchronous FIFO	Interne	Passing Juice
Formally Verifying Asynchronous Components	Interne	Passing Juice
A Slow but Symmetric FIR Filter Implementation	Interne	Passing Juice
Updated Projects List	Interne	Passing Juice
Aggregating verified modules together	Interne	Passing Juice
ZipTimer: A simple countdown timer	Interne	Passing Juice
Formally Verifying an Asynchronous Reset	Interne	Passing Juice
What would you like to see on the ZipCPU blog?	Interne	Passing Juice
Will formal methods ever find a bug in a working CPU?	Interne	Passing Juice
Resurrection Day!	Interne	Passing Juice
Quadratic fits are entirely inappropriate for DSP	Interne	Passing Juice
Pipelining a Prefetch	Interne	Passing Juice
Is formal really all that hard?	Interne	Passing Juice
An Exercise in using Formal Induction	Interne	Passing Juice
Want to use ZBasic? Let's have some fun--no actual FPGA required!	Interne	Passing Juice
Debugging a Cyclone-V	Interne	Passing Juice
ZipCPU toolchain and initial test	Interne	Passing Juice
Updating ZipCPU files	Interne	Passing Juice
Interpolation is just a special type of convolution	Interne	Passing Juice
A Quick Introduction to the ZipCPU Instruction Set	Interne	Passing Juice
Top 10 ZipCPU blog posts for 2017	Interne	Passing Juice
A better filter implementation for slower signals	Interne	Passing Juice
Mystery post: The ugliest bug I've ever encountered	Interne	Passing Juice
Arrow's Max-1000: A gem for all the wrong reasons	Interne	Passing Juice
Building a Simple Logic PLL	Interne	Passing Juice
Building a Numerically Controlled Oscillator	Interne	Passing Juice
Testing the fast, generic FIR filter	Interne	Passing Juice
Thank you!	Interne	Passing Juice
Measuring the frequency response of a filter under test	Interne	Passing Juice
Building a prefetch module for the ZipCPU	Interne	Passing Juice
Generating more than one bit at a time with an LFSR	Interne	Passing Juice
An example LFSR	Interne	Passing Juice
A Configurable Signal Delay Element	Interne	Passing Juice
Building Formal Assumptions to Describe Wishbone Behaviour	Interne	Passing Juice
The Interface to a Generic Filtering Testbench	Interne	Passing Juice
Good Software Engineering Principles Apply to Students Too	Interne	Passing Juice
Generating Pseudo-Random Numbers on an FPGA	Interne	Passing Juice
Some Simple Clock-Domain Crossing Solutions	Interne	Passing Juice
My first experience with Formal Methods	Interne	Passing Juice
Just some notes to new readers of the ZipCPU blog	Interne	Passing Juice
Implementing the Moving Average (Boxcar) filter	Interne	Passing Juice
FPGAs vs ASICs	Interne	Passing Juice
It's all about the interfaces	Interne	Passing Juice
Using AutoFPGA to connect simple registers to a debugging bus	Interne	Passing Juice
A Brief Introduction to AutoFPGA	Interne	Passing Juice
A CORDIC testbench	Interne	Passing Juice
A Cheaper Fast FIR Filter	Interne	Passing Juice
Understanding the effects of Quantization	Interne	Passing Juice
Clocks for Software Engineers	Interne	Passing Juice
Demonstrating the improved PWM waveform	Interne	Passing Juice
Building a high speed Finite Impulse Response (FIR) Digital Filter	Interne	Passing Juice
Even I get stuck in FPGA Hell	Interne	Passing Juice
Glad I went to ORCONF	Interne	Passing Juice
Off to ORCONF-2017!	Interne	Passing Juice
Reinventing PWM	Interne	Passing Juice
Big Money Engineering Integrity	Interne	Passing Juice
CORDIC part two: rectangular to polar conversion	Interne	Passing Juice
Using a CORDIC to calculate sines and cosines in an FPGA	Interne	Passing Juice
Building a quarter sine-wave lookup table	Interne	Passing Juice
Debugging your soft-core CPU within an FPGA	Interne	Passing Juice
The ZipCPU's pipeline logic	Interne	Passing Juice
Rules for new FPGA designers	Interne	Passing Juice
Two of the Simplest Digital filters	Interne	Passing Juice
Strategies for pipelining logic	Interne	Passing Juice
What would cause you to lie?	Interne	Passing Juice
A Simple ALU, drawn from the ZipCPU	Interne	Passing Juice
Series: Debouncing in Digital Logic	Interne	Passing Juice
Using a debug-bus to Measure Bouncing	Interne	Passing Juice
Measuring Contact Bounce	Interne	Passing Juice
How to eliminate button bounces with digital logic	Interne	Passing Juice
Visualizing Contact Bounce	Interne	Passing Juice
ZipCPU Advertising	Interne	Passing Juice
Writing your own VCD File	Interne	Passing Juice
Linear Interpolation	Interne	Passing Juice
Getting the basic FIFO right	Interne	Passing Juice
Windows FPGA designers may not need a Linux machine ... yet	Interne	Passing Juice
How to build a simulation based debugger for your own soft-core CPU	Interne	Passing Juice
How to Debug a DSP algorithm	Interne	Passing Juice
Rounding Numbers without Adding a Bias	Interne	Passing Juice
Bit growth in FPGA arithmetic	Interne	Passing Juice
A Basic Upsampling Linear Interpolator	Interne	Passing Juice
Verilator doesn't find everything (today)	Interne	Passing Juice
Design Needs when Debugging a SoftCore CPU	Interne	Passing Juice
The simplest sine wave generator within an FPGA	Interne	Passing Juice
Getting Started with the Wishbone Scope	Interne	Passing Juice
Finishing off the debugging bus: building a software interface	Interne	Passing Juice
Why you want a debug port into your FPGA	Interne	Passing Juice
Simulating an FPGA through the debugging interface	Interne	Passing Juice
My own FPGA debugging philosophy	Interne	Passing Juice
Building a very simple wishbone interconnect	Interne	Passing Juice
Taking a New Look at Verilator	Interne	Passing Juice
Putting our Debugging Bus RTL Components Together	Interne	Passing Juice
Sending bus idle notifications down the line	Interne	Passing Juice
Why Use a Network Interface to your FPGA	Interne	Passing Juice
Support me on Patreon	Interne	Passing Juice
The debugging bus: a goal for FPGA interaction	Interne	Passing Juice
Adding interrupt reporting to our debugging bus	Interne	Passing Juice
How to send our bus results back out the serial port	Interne	Passing Juice
No PI for you	Interne	Passing Juice
How to create bus command words, from a 7-bit data stream	Interne	Passing Juice
Minimizing FPGA Resource Utilization	Interne	Passing Juice
A College Student's Response to the FPGA Design Process	Interne	Passing Juice
Building a Simple Wishbone Master	Interne	Passing Juice
Building A Simple In-Circuit Logic Analyzer	Interne	Passing Juice
Nearest Neighbor Interpolation	Interne	Passing Juice
An Overview of a Wishbone-UART Bridge	Interne	Passing Juice
Campus Sidewalks and FPGA Design	Interne	Passing Juice
Controlling Timing within an FPGA	Interne	Passing Juice
The Actual FPGA Design Process	Interne	Passing Juice
Building a simple wishbone slave	Interne	Passing Juice
Bus Select Lines	Interne	Passing Juice
FFT debugging	Interne	Passing Juice
Debugging an FPGA through the serial port--first steps	Interne	Passing Juice
That first serial port: Debugging when you are blind	Interne	Passing Juice
Building a simple bus	Interne	Passing Juice
Moving to memory	Interne	Passing Juice
A Vision for Controlling FPGA Logic	Interne	Passing Juice
Which comes first: the CPU or the peripherals?	Interne	Passing Juice
Knight Rider	Interne	Passing Juice
FPGA Hell	Interne	Passing Juice
Blinky	Interne	Passing Juice
Most common Digilent FPGA support requests	Interne	Passing Juice
Cannot be done	Interne	Passing Juice
Welcome to the ZipCPU blog!	Interne	Passing Juice
via RSS	Interne	Passing Juice

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