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The ZipCPU by Gisselquist Technology

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The ZipCPU by Gisselquist Technology

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The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.

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Titulos

H1	H2	H3	H4	H5	H6
1	270	0	0	0	0

[H1] Blog Posts
[H2] Device Clock Generation
[H2] Quiz #24: Is there an AXI bug here?
[H2] Comparing the Xilinx MIG with an open source DDR3 controller
[H2] Wrap addressing
[H2] Your problem is not AXI
[H2] My Personal Journey in Verification
[H2] Debugging video from across the ocean
[H2] Bringing up Kimos
[H2] Chasing resets
[H2] 2023, Year in review
[H2] An Overview of a 10Gb Ethernet Switch
[H2] SDIO RX: Bugs found w/ Formal methods
[H2] Using a Verilog task to simulate a packet generator for an SDIO controller
[H2] Introducing the ZipCPU v3.0
[H2] What is a Virtual Packet FIFO?
[H2] What is a SwiC?
[H2] Debugging the Hard Stuff
[H2] Your soft-core CPU won't boot. Where should you start debugging?
[H2] Thanksgiving! I have much to be thankful for
[H2] Quiz #23: Can this assertion fail?
[H2] A first lesson in sales pitches: Honesty
[H2] Quiz #22: Handling cover failures
[H2] Measuring the Steps to Design Checkoff
[H2] Assignment delay's and Verilog's wait statement
[H2] It's not my fault! Your code is broken.
[H2] Protocol Design for Network Debugging
[H2] Quiz #21: Verifying all configurations of a design
[H2] ZipCPU Lesson: If it's not tested, it doesn't work.
[H2] A Coming Economic Downturn? or Worse?
[H2] Quiz #20: Using $stable in a multiclock environment
[H2] Learning AXI: Where to start?
[H2] Bringing up a new piece of hardware -- what can go wrong?
[H2] Rethinking Video with AXI video streams
[H2] AXI Stream is broken
[H2] 2020 and 2021 in review
[H2] Quiz #19: Using disable iff in a concurrent assertion
[H2] Creating a Simple AXI-Lite Master for the Hexbus
[H2] Envisioning the Ultimate I2C Controller
[H2] Clock Gating
[H2] Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
[H2] Quiz #18: Failures in clocked immediate assertions
[H2] AXI Handshaking Rules
[H2] Measuring AXI latency and throughput performance
[H2] Quiz #17: Induction failures
[H2] The other half of the Gospel
[H2] CPU based simulation, first thoughts
[H2] Quiz #16: Immediate assertions in the presence of asynchronous resets
[H2] Building a Better Verilog Multiply for the ZipCPU
[H2] Examples of AXI4 bus masters
[H2] Quiz #15: Pass-through memory
[H2] Fixing Xilinx's Broken AXI-lite Design in VHDL
[H2] Building a Simple AXI-lite Memory Controller
[H2] Common AXI Themes on Xilinx's Forum
[H2] Whatever happened to the ZipOS?
[H2] Lessons learned while building an ASIC design
[H2] The FPGA designer who didn't get the job
[H2] Ultimate Logic
[H2] Quiz #14: Two nearly identical frequencies
[H2] Formally verifying register handling
[H2] Is it possible to make a living as a solo digital design engineer?
[H2] Spectrograms need Window Functions
[H2] A fun Friday evening--verifying an AXI-lite slave
[H2] Moving values and strobes cross clock domains
[H2] Quiz #13: Temporal assertion equivalences
[H2] Run length encoding an AXI stream
[H2] Driving an output on both edges of the clock
[H2] Building a Downsampling Filter
[H2] I have a brand new piece of IP. How shall I verify it?
[H2] Measuring clock speed
[H2] The hard part of building a bursting AXI Master
[H2] Four keys to getting your design to work the first time
[H2] Quiz #12: Catching extraneous acknowledgments
[H2] Building a Protocol Firewall
[H2] Debugging AXI Streams
[H2] Adding an AXI-Lite interface to your Verilator test script
[H2] Re: What does your design flow look like?
[H2] Building a basic AXI Master
[H2] Cheap Spectral Estimation
[H2] Locally resetting an AXI component
[H2] Adjusting our logic PLL to handle I&Q
[H2] Buidilng an AXI-Lite slave the easy way
[H2] The Faith of a Mustard Seed
[H2] A Histogram Gone Bad
[H2] Quiz #11: Induction and clock enables
[H2] Quiz #10: Checking stall conditions
[H2] Lessons in Hardware Reuse
[H2] 2019: AXI Meets Formal Verification
[H2] The Christmas Gospel
[H2] Using a Histogram to Debug A/D Data Streams
[H2] Quiz #9: Immediate assertions midst blocking assignments
[H2] Quiz #8: Will this pass a bounded model check?
[H2] The ZipCPU meets blinky
[H2] Formally Verifying a General Purpose Ultra-Micro Controller
[H2] Quiz #7: Returning to $past() and our counter again
[H2] Putting the pieces together to build a data recorder
[H2] Is formal verfication enough, or is simulation required?
[H2] Quiz #6: Synchronous logic in Asynchronous contexts
[H2] AXI Verification, the story so far
[H2] Understanding AutoFPGA's address assignment algorithm
[H2] Quiz #5: Immediate vs Concurrent Assertions
[H2] Connecting lots of slaves to a bus without using a lot of logic
[H2] Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
[H2] Technology Debt and AutoFPGA, the bill just came due
[H2] Xilinx deleted this post
[H2] Quiz #3: Will formal verification prove this counter keeps its bounds?
[H2] Planning an Intermediate Design Tutorial
[H2] Quiz #2: Will this counter pass formal verification?
[H2] Quiz #1: Will the assertion below ever fail?
[H2] Just how long does a formal proof take to finish?
[H2] Lessons learned while building crossbar interconnects
[H2] Breaking all the rules to create an arbitrary clock signal
[H2] Building the perfect AXI4 slave
[H2] Building a Skid Buffer for AXI processing
[H2] Examining Xilinx's AXI demonstration core
[H2] Understanding AXI Addressing
[H2] Project Ideas: PMod AMP2
[H2] Applying Formal Methods to the Events of the Resurrection
[H2] The most common AXI mistake
[H2] The ZipCPU's Interrupt Controller
[H2] Logic usage and decoding return results with cascaded multiplexers
[H2] Building a universal QSPI flash controller
[H2] Introducing the ArrowZip ZipCPU design, featuring the Max-1000
[H2] Using Sequence Properties to Verify a Serial Port Transmitter
[H2] Why does blinky make a CPU appear to be so slow?
[H2] Debugging a CPU
[H2] Building a custom yet functional AXI-lite slave
[H2] ZipCPU highlights from 2018
[H2] Using a formal property file to verify an AXI-lite peripheral
[H2] AutoFPGA's linker script support gets an update
[H2] Makefiles for formal proofs with SymbiYosys
[H2] Swapping assumptions and assertions doesn't work
[H2] Building a video controller: it's just a pair of counters
[H2] Accessing the registers of a SoC+FPGA
[H2] Taking a look at the TinyFPGA BX
[H2] To my new readers and my new twitter followers, welcome!
[H2] An Open Source Pipelined FFT Generator
[H2] It's time for ORCONF 2018!
[H2] My design works in simulation, but not in hardware. Can formal methods help me?
[H2] Handling multiple clocks with Verilator
[H2] RE: Building a simulation for my design? What does that mean?
[H2] How to build a SPI Flash Controller for an FPGA
[H2] Reasons why Synthesis might not match Simulation
[H2] Why I like Formal: the ZipCPU and the ICO board
[H2] What does Formal Development look like in Practice?
[H2] Formally Verifying Memory and Cache Components
[H2] Crossing clock domains with an Asynchronous FIFO
[H2] Formally Verifying Asynchronous Components
[H2] A Slow but Symmetric FIR Filter Implementation
[H2] Updated Projects List
[H2] Aggregating verified modules together
[H2] ZipTimer: A simple countdown timer
[H2] Formally Verifying an Asynchronous Reset
[H2] What would you like to see on the ZipCPU blog?
[H2] Will formal methods ever find a bug in a working CPU?
[H2] Resurrection Day!
[H2] Quadratic fits are entirely inappropriate for DSP
[H2] Pipelining a Prefetch
[H2] Is formal really all that hard?
[H2] An Exercise in using Formal Induction
[H2] Want to use ZBasic? Let's have some fun--no actual FPGA required!
[H2] Debugging a Cyclone-V
[H2] ZipCPU toolchain and initial test
[H2] Updating ZipCPU files
[H2] Interpolation is just a special type of convolution
[H2] A Quick Introduction to the ZipCPU Instruction Set
[H2] Top 10 ZipCPU blog posts for 2017
[H2] A better filter implementation for slower signals
[H2] Mystery post: The ugliest bug I've ever encountered
[H2] Arrow's Max-1000: A gem for all the wrong reasons
[H2] Building a Simple Logic PLL
[H2] Building a Numerically Controlled Oscillator
[H2] Testing the fast, generic FIR filter
[H2] Thank you!
[H2] Measuring the frequency response of a filter under test
[H2] Building a prefetch module for the ZipCPU
[H2] Generating more than one bit at a time with an LFSR
[H2] An example LFSR
[H2] A Configurable Signal Delay Element
[H2] Building Formal Assumptions to Describe Wishbone Behaviour
[H2] The Interface to a Generic Filtering Testbench
[H2] Good Software Engineering Principles Apply to Students Too
[H2] Generating Pseudo-Random Numbers on an FPGA
[H2] Some Simple Clock-Domain Crossing Solutions
[H2] My first experience with Formal Methods
[H2] Just some notes to new readers of the ZipCPU blog
[H2] Implementing the Moving Average (Boxcar) filter
[H2] FPGAs vs ASICs
[H2] It's all about the interfaces
[H2] Using AutoFPGA to connect simple registers to a debugging bus
[H2] A Brief Introduction to AutoFPGA
[H2] A CORDIC testbench
[H2] A Cheaper Fast FIR Filter
[H2] Understanding the effects of Quantization
[H2] Clocks for Software Engineers
[H2] Demonstrating the improved PWM waveform
[H2] Building a high speed Finite Impulse Response (FIR) Digital Filter
[H2] Even I get stuck in FPGA Hell
[H2] Glad I went to ORCONF
[H2] Off to ORCONF-2017!
[H2] Reinventing PWM
[H2] Big Money Engineering Integrity
[H2] CORDIC part two: rectangular to polar conversion
[H2] Using a CORDIC to calculate sines and cosines in an FPGA
[H2] Building a quarter sine-wave lookup table
[H2] Debugging your soft-core CPU within an FPGA
[H2] The ZipCPU's pipeline logic
[H2] Rules for new FPGA designers
[H2] Two of the Simplest Digital filters
[H2] Strategies for pipelining logic
[H2] What would cause you to lie?
[H2] A Simple ALU, drawn from the ZipCPU
[H2] Series: Debouncing in Digital Logic
[H2] Using a debug-bus to Measure Bouncing
[H2] Measuring Contact Bounce
[H2] How to eliminate button bounces with digital logic
[H2] Visualizing Contact Bounce
[H2] ZipCPU Advertising
[H2] Writing your own VCD File
[H2] Linear Interpolation
[H2] Getting the basic FIFO right
[H2] Windows FPGA designers may not need a Linux machine ... yet
[H2] How to build a simulation based debugger for your own soft-core CPU
[H2] How to Debug a DSP algorithm
[H2] Rounding Numbers without Adding a Bias
[H2] Bit growth in FPGA arithmetic
[H2] A Basic Upsampling Linear Interpolator
[H2] Verilator doesn't find everything (today)
[H2] Design Needs when Debugging a SoftCore CPU
[H2] The simplest sine wave generator within an FPGA
[H2] Getting Started with the Wishbone Scope
[H2] Finishing off the debugging bus: building a software interface
[H2] Why you want a debug port into your FPGA
[H2] Simulating an FPGA through the debugging interface
[H2] My own FPGA debugging philosophy
[H2] Building a very simple wishbone interconnect
[H2] Taking a New Look at Verilator
[H2] Putting our Debugging Bus RTL Components Together
[H2] Sending bus idle notifications down the line
[H2] Why Use a Network Interface to your FPGA
[H2] Support me on Patreon
[H2] The debugging bus: a goal for FPGA interaction
[H2] Adding interrupt reporting to our debugging bus
[H2] How to send our bus results back out the serial port
[H2] No PI for you
[H2] How to create bus command words, from a 7-bit data stream
[H2] Minimizing FPGA Resource Utilization
[H2] A College Student's Response to the FPGA Design Process
[H2] Building a Simple Wishbone Master
[H2] Building A Simple In-Circuit Logic Analyzer
[H2] Nearest Neighbor Interpolation
[H2] An Overview of a Wishbone-UART Bridge
[H2] Campus Sidewalks and FPGA Design
[H2] Controlling Timing within an FPGA
[H2] The Actual FPGA Design Process
[H2] Building a simple wishbone slave
[H2] Bus Select Lines
[H2] FFT debugging
[H2] Debugging an FPGA through the serial port--first steps
[H2] That first serial port: Debugging when you are blind
[H2] Building a simple bus
[H2] Moving to memory
[H2] A Vision for Controlling FPGA Logic
[H2] Which comes first: the CPU or the peripherals?
[H2] Knight Rider
[H2] FPGA Hell
[H2] Blinky
[H2] Most common Digilent FPGA support requests
[H2] Cannot be done
[H2] Welcome to the ZipCPU blog!
[H2] The ZipCPU by Gisselquist Technology

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Ancla	Tipo	Jugo
About Us	Interna	Pasando Jugo
FPGA Hell	Interna	Pasando Jugo
Tutorial	Interna	Pasando Jugo
Formal training	Interna	Pasando Jugo
Quizzes	Interna	Pasando Jugo
Projects	Interna	Pasando Jugo
Site Index	Interna	Pasando Jugo
Device Clock Generation	Interna	Pasando Jugo
Quiz #24: Is there an AXI bug here?	Interna	Pasando Jugo
Comparing the Xilinx MIG with an open source DDR3 controller	Interna	Pasando Jugo
Wrap addressing	Interna	Pasando Jugo
Your problem is not AXI	Interna	Pasando Jugo
My Personal Journey in Verification	Interna	Pasando Jugo
Debugging video from across the ocean	Interna	Pasando Jugo
Bringing up Kimos	Interna	Pasando Jugo
Chasing resets	Interna	Pasando Jugo
2023, Year in review	Interna	Pasando Jugo
An Overview of a 10Gb Ethernet Switch	Interna	Pasando Jugo
SDIO RX: Bugs found w/ Formal methods	Interna	Pasando Jugo
Using a Verilog task to simulate a packet generator for an SDIO controller	Interna	Pasando Jugo
Introducing the ZipCPU v3.0	Interna	Pasando Jugo
What is a Virtual Packet FIFO?	Interna	Pasando Jugo
What is a SwiC?	Interna	Pasando Jugo
Debugging the Hard Stuff	Interna	Pasando Jugo
Your soft-core CPU won't boot. Where should you start debugging?	Interna	Pasando Jugo
Thanksgiving! I have much to be thankful for	Interna	Pasando Jugo
Quiz #23: Can this assertion fail?	Interna	Pasando Jugo
A first lesson in sales pitches: Honesty	Interna	Pasando Jugo
Quiz #22: Handling cover failures	Interna	Pasando Jugo
Measuring the Steps to Design Checkoff	Interna	Pasando Jugo
Assignment delay's and Verilog's wait statement	Interna	Pasando Jugo
It's not my fault! Your code is broken.	Interna	Pasando Jugo
Protocol Design for Network Debugging	Interna	Pasando Jugo
Quiz #21: Verifying all configurations of a design	Interna	Pasando Jugo
ZipCPU Lesson: If it's not tested, it doesn't work.	Interna	Pasando Jugo
A Coming Economic Downturn? or Worse?	Interna	Pasando Jugo
Quiz #20: Using $stable in a multiclock environment	Interna	Pasando Jugo
Learning AXI: Where to start?	Interna	Pasando Jugo
Bringing up a new piece of hardware -- what can go wrong?	Interna	Pasando Jugo
Rethinking Video with AXI video streams	Interna	Pasando Jugo
AXI Stream is broken	Interna	Pasando Jugo
2020 and 2021 in review	Interna	Pasando Jugo
Quiz #19: Using disable iff in a concurrent assertion	Interna	Pasando Jugo
Creating a Simple AXI-Lite Master for the Hexbus	Interna	Pasando Jugo
Envisioning the Ultimate I2C Controller	Interna	Pasando Jugo
Clock Gating	Interna	Pasando Jugo
Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4	Interna	Pasando Jugo
Quiz #18: Failures in clocked immediate assertions	Interna	Pasando Jugo
AXI Handshaking Rules	Interna	Pasando Jugo
Measuring AXI latency and throughput performance	Interna	Pasando Jugo
Quiz #17: Induction failures	Interna	Pasando Jugo
The other half of the Gospel	Interna	Pasando Jugo
CPU based simulation, first thoughts	Interna	Pasando Jugo
Quiz #16: Immediate assertions in the presence of asynchronous resets	Interna	Pasando Jugo
Building a Better Verilog Multiply for the ZipCPU	Interna	Pasando Jugo
Examples of AXI4 bus masters	Interna	Pasando Jugo
Quiz #15: Pass-through memory	Interna	Pasando Jugo
Fixing Xilinx's Broken AXI-lite Design in VHDL	Interna	Pasando Jugo
Building a Simple AXI-lite Memory Controller	Interna	Pasando Jugo
Common AXI Themes on Xilinx's Forum	Interna	Pasando Jugo
Whatever happened to the ZipOS?	Interna	Pasando Jugo
Lessons learned while building an ASIC design	Interna	Pasando Jugo
The FPGA designer who didn't get the job	Interna	Pasando Jugo
Ultimate Logic	Interna	Pasando Jugo
Quiz #14: Two nearly identical frequencies	Interna	Pasando Jugo
Formally verifying register handling	Interna	Pasando Jugo
Is it possible to make a living as a solo digital design engineer?	Interna	Pasando Jugo
Spectrograms need Window Functions	Interna	Pasando Jugo
A fun Friday evening--verifying an AXI-lite slave	Interna	Pasando Jugo
Moving values and strobes cross clock domains	Interna	Pasando Jugo
Quiz #13: Temporal assertion equivalences	Interna	Pasando Jugo
Run length encoding an AXI stream	Interna	Pasando Jugo
Driving an output on both edges of the clock	Interna	Pasando Jugo
Building a Downsampling Filter	Interna	Pasando Jugo
I have a brand new piece of IP. How shall I verify it?	Interna	Pasando Jugo
Measuring clock speed	Interna	Pasando Jugo
The hard part of building a bursting AXI Master	Interna	Pasando Jugo
Four keys to getting your design to work the first time	Interna	Pasando Jugo
Quiz #12: Catching extraneous acknowledgments	Interna	Pasando Jugo
Building a Protocol Firewall	Interna	Pasando Jugo
Debugging AXI Streams	Interna	Pasando Jugo
Adding an AXI-Lite interface to your Verilator test script	Interna	Pasando Jugo
Re: What does your design flow look like?	Interna	Pasando Jugo
Building a basic AXI Master	Interna	Pasando Jugo
Cheap Spectral Estimation	Interna	Pasando Jugo
Locally resetting an AXI component	Interna	Pasando Jugo
Adjusting our logic PLL to handle I&Q	Interna	Pasando Jugo
Buidilng an AXI-Lite slave the easy way	Interna	Pasando Jugo
The Faith of a Mustard Seed	Interna	Pasando Jugo
A Histogram Gone Bad	Interna	Pasando Jugo
Quiz #11: Induction and clock enables	Interna	Pasando Jugo
Quiz #10: Checking stall conditions	Interna	Pasando Jugo
Lessons in Hardware Reuse	Interna	Pasando Jugo
2019: AXI Meets Formal Verification	Interna	Pasando Jugo
The Christmas Gospel	Interna	Pasando Jugo
Using a Histogram to Debug A/D Data Streams	Interna	Pasando Jugo
Quiz #9: Immediate assertions midst blocking assignments	Interna	Pasando Jugo
Quiz #8: Will this pass a bounded model check?	Interna	Pasando Jugo
The ZipCPU meets blinky	Interna	Pasando Jugo
Formally Verifying a General Purpose Ultra-Micro Controller	Interna	Pasando Jugo
Quiz #7: Returning to $past() and our counter again	Interna	Pasando Jugo
Putting the pieces together to build a data recorder	Interna	Pasando Jugo
Is formal verfication enough, or is simulation required?	Interna	Pasando Jugo
Quiz #6: Synchronous logic in Asynchronous contexts	Interna	Pasando Jugo
AXI Verification, the story so far	Interna	Pasando Jugo
Understanding AutoFPGA's address assignment algorithm	Interna	Pasando Jugo
Quiz #5: Immediate vs Concurrent Assertions	Interna	Pasando Jugo
Connecting lots of slaves to a bus without using a lot of logic	Interna	Pasando Jugo
Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?	Interna	Pasando Jugo
Technology Debt and AutoFPGA, the bill just came due	Interna	Pasando Jugo
Xilinx deleted this post	Interna	Pasando Jugo
Quiz #3: Will formal verification prove this counter keeps its bounds?	Interna	Pasando Jugo
Planning an Intermediate Design Tutorial	Interna	Pasando Jugo
Quiz #2: Will this counter pass formal verification?	Interna	Pasando Jugo
Quiz #1: Will the assertion below ever fail?	Interna	Pasando Jugo
Just how long does a formal proof take to finish?	Interna	Pasando Jugo
Lessons learned while building crossbar interconnects	Interna	Pasando Jugo
Breaking all the rules to create an arbitrary clock signal	Interna	Pasando Jugo
Building the perfect AXI4 slave	Interna	Pasando Jugo
Building a Skid Buffer for AXI processing	Interna	Pasando Jugo
Examining Xilinx's AXI demonstration core	Interna	Pasando Jugo
Understanding AXI Addressing	Interna	Pasando Jugo
Project Ideas: PMod AMP2	Interna	Pasando Jugo
Applying Formal Methods to the Events of the Resurrection	Interna	Pasando Jugo
The most common AXI mistake	Interna	Pasando Jugo
The ZipCPU's Interrupt Controller	Interna	Pasando Jugo
Logic usage and decoding return results with cascaded multiplexers	Interna	Pasando Jugo
Building a universal QSPI flash controller	Interna	Pasando Jugo
Introducing the ArrowZip ZipCPU design, featuring the Max-1000	Interna	Pasando Jugo
Using Sequence Properties to Verify a Serial Port Transmitter	Interna	Pasando Jugo
Why does blinky make a CPU appear to be so slow?	Interna	Pasando Jugo
Debugging a CPU	Interna	Pasando Jugo
Building a custom yet functional AXI-lite slave	Interna	Pasando Jugo
ZipCPU highlights from 2018	Interna	Pasando Jugo
Using a formal property file to verify an AXI-lite peripheral	Interna	Pasando Jugo
AutoFPGA's linker script support gets an update	Interna	Pasando Jugo
Makefiles for formal proofs with SymbiYosys	Interna	Pasando Jugo
Swapping assumptions and assertions doesn't work	Interna	Pasando Jugo
Building a video controller: it's just a pair of counters	Interna	Pasando Jugo
Accessing the registers of a SoC+FPGA	Interna	Pasando Jugo
Taking a look at the TinyFPGA BX	Interna	Pasando Jugo
To my new readers and my new twitter followers, welcome!	Interna	Pasando Jugo
An Open Source Pipelined FFT Generator	Interna	Pasando Jugo
It's time for ORCONF 2018!	Interna	Pasando Jugo
My design works in simulation, but not in hardware. Can formal methods help me?	Interna	Pasando Jugo
Handling multiple clocks with Verilator	Interna	Pasando Jugo
RE: Building a simulation for my design? What does that mean?	Interna	Pasando Jugo
How to build a SPI Flash Controller for an FPGA	Interna	Pasando Jugo
Reasons why Synthesis might not match Simulation	Interna	Pasando Jugo
Why I like Formal: the ZipCPU and the ICO board	Interna	Pasando Jugo
What does Formal Development look like in Practice?	Interna	Pasando Jugo
Formally Verifying Memory and Cache Components	Interna	Pasando Jugo
Crossing clock domains with an Asynchronous FIFO	Interna	Pasando Jugo
Formally Verifying Asynchronous Components	Interna	Pasando Jugo
A Slow but Symmetric FIR Filter Implementation	Interna	Pasando Jugo
Updated Projects List	Interna	Pasando Jugo
Aggregating verified modules together	Interna	Pasando Jugo
ZipTimer: A simple countdown timer	Interna	Pasando Jugo
Formally Verifying an Asynchronous Reset	Interna	Pasando Jugo
What would you like to see on the ZipCPU blog?	Interna	Pasando Jugo
Will formal methods ever find a bug in a working CPU?	Interna	Pasando Jugo
Resurrection Day!	Interna	Pasando Jugo
Quadratic fits are entirely inappropriate for DSP	Interna	Pasando Jugo
Pipelining a Prefetch	Interna	Pasando Jugo
Is formal really all that hard?	Interna	Pasando Jugo
An Exercise in using Formal Induction	Interna	Pasando Jugo
Want to use ZBasic? Let's have some fun--no actual FPGA required!	Interna	Pasando Jugo
Debugging a Cyclone-V	Interna	Pasando Jugo
ZipCPU toolchain and initial test	Interna	Pasando Jugo
Updating ZipCPU files	Interna	Pasando Jugo
Interpolation is just a special type of convolution	Interna	Pasando Jugo
A Quick Introduction to the ZipCPU Instruction Set	Interna	Pasando Jugo
Top 10 ZipCPU blog posts for 2017	Interna	Pasando Jugo
A better filter implementation for slower signals	Interna	Pasando Jugo
Mystery post: The ugliest bug I've ever encountered	Interna	Pasando Jugo
Arrow's Max-1000: A gem for all the wrong reasons	Interna	Pasando Jugo
Building a Simple Logic PLL	Interna	Pasando Jugo
Building a Numerically Controlled Oscillator	Interna	Pasando Jugo
Testing the fast, generic FIR filter	Interna	Pasando Jugo
Thank you!	Interna	Pasando Jugo
Measuring the frequency response of a filter under test	Interna	Pasando Jugo
Building a prefetch module for the ZipCPU	Interna	Pasando Jugo
Generating more than one bit at a time with an LFSR	Interna	Pasando Jugo
An example LFSR	Interna	Pasando Jugo
A Configurable Signal Delay Element	Interna	Pasando Jugo
Building Formal Assumptions to Describe Wishbone Behaviour	Interna	Pasando Jugo
The Interface to a Generic Filtering Testbench	Interna	Pasando Jugo
Good Software Engineering Principles Apply to Students Too	Interna	Pasando Jugo
Generating Pseudo-Random Numbers on an FPGA	Interna	Pasando Jugo
Some Simple Clock-Domain Crossing Solutions	Interna	Pasando Jugo
My first experience with Formal Methods	Interna	Pasando Jugo
Just some notes to new readers of the ZipCPU blog	Interna	Pasando Jugo
Implementing the Moving Average (Boxcar) filter	Interna	Pasando Jugo
FPGAs vs ASICs	Interna	Pasando Jugo
It's all about the interfaces	Interna	Pasando Jugo
Using AutoFPGA to connect simple registers to a debugging bus	Interna	Pasando Jugo
A Brief Introduction to AutoFPGA	Interna	Pasando Jugo
A CORDIC testbench	Interna	Pasando Jugo
A Cheaper Fast FIR Filter	Interna	Pasando Jugo
Understanding the effects of Quantization	Interna	Pasando Jugo
Clocks for Software Engineers	Interna	Pasando Jugo
Demonstrating the improved PWM waveform	Interna	Pasando Jugo
Building a high speed Finite Impulse Response (FIR) Digital Filter	Interna	Pasando Jugo
Even I get stuck in FPGA Hell	Interna	Pasando Jugo
Glad I went to ORCONF	Interna	Pasando Jugo
Off to ORCONF-2017!	Interna	Pasando Jugo
Reinventing PWM	Interna	Pasando Jugo
Big Money Engineering Integrity	Interna	Pasando Jugo
CORDIC part two: rectangular to polar conversion	Interna	Pasando Jugo
Using a CORDIC to calculate sines and cosines in an FPGA	Interna	Pasando Jugo
Building a quarter sine-wave lookup table	Interna	Pasando Jugo
Debugging your soft-core CPU within an FPGA	Interna	Pasando Jugo
The ZipCPU's pipeline logic	Interna	Pasando Jugo
Rules for new FPGA designers	Interna	Pasando Jugo
Two of the Simplest Digital filters	Interna	Pasando Jugo
Strategies for pipelining logic	Interna	Pasando Jugo
What would cause you to lie?	Interna	Pasando Jugo
A Simple ALU, drawn from the ZipCPU	Interna	Pasando Jugo
Series: Debouncing in Digital Logic	Interna	Pasando Jugo
Using a debug-bus to Measure Bouncing	Interna	Pasando Jugo
Measuring Contact Bounce	Interna	Pasando Jugo
How to eliminate button bounces with digital logic	Interna	Pasando Jugo
Visualizing Contact Bounce	Interna	Pasando Jugo
ZipCPU Advertising	Interna	Pasando Jugo
Writing your own VCD File	Interna	Pasando Jugo
Linear Interpolation	Interna	Pasando Jugo
Getting the basic FIFO right	Interna	Pasando Jugo
Windows FPGA designers may not need a Linux machine ... yet	Interna	Pasando Jugo
How to build a simulation based debugger for your own soft-core CPU	Interna	Pasando Jugo
How to Debug a DSP algorithm	Interna	Pasando Jugo
Rounding Numbers without Adding a Bias	Interna	Pasando Jugo
Bit growth in FPGA arithmetic	Interna	Pasando Jugo
A Basic Upsampling Linear Interpolator	Interna	Pasando Jugo
Verilator doesn't find everything (today)	Interna	Pasando Jugo
Design Needs when Debugging a SoftCore CPU	Interna	Pasando Jugo
The simplest sine wave generator within an FPGA	Interna	Pasando Jugo
Getting Started with the Wishbone Scope	Interna	Pasando Jugo
Finishing off the debugging bus: building a software interface	Interna	Pasando Jugo
Why you want a debug port into your FPGA	Interna	Pasando Jugo
Simulating an FPGA through the debugging interface	Interna	Pasando Jugo
My own FPGA debugging philosophy	Interna	Pasando Jugo
Building a very simple wishbone interconnect	Interna	Pasando Jugo
Taking a New Look at Verilator	Interna	Pasando Jugo
Putting our Debugging Bus RTL Components Together	Interna	Pasando Jugo
Sending bus idle notifications down the line	Interna	Pasando Jugo
Why Use a Network Interface to your FPGA	Interna	Pasando Jugo
Support me on Patreon	Interna	Pasando Jugo
The debugging bus: a goal for FPGA interaction	Interna	Pasando Jugo
Adding interrupt reporting to our debugging bus	Interna	Pasando Jugo
How to send our bus results back out the serial port	Interna	Pasando Jugo
No PI for you	Interna	Pasando Jugo
How to create bus command words, from a 7-bit data stream	Interna	Pasando Jugo
Minimizing FPGA Resource Utilization	Interna	Pasando Jugo
A College Student's Response to the FPGA Design Process	Interna	Pasando Jugo
Building a Simple Wishbone Master	Interna	Pasando Jugo
Building A Simple In-Circuit Logic Analyzer	Interna	Pasando Jugo
Nearest Neighbor Interpolation	Interna	Pasando Jugo
An Overview of a Wishbone-UART Bridge	Interna	Pasando Jugo
Campus Sidewalks and FPGA Design	Interna	Pasando Jugo
Controlling Timing within an FPGA	Interna	Pasando Jugo
The Actual FPGA Design Process	Interna	Pasando Jugo
Building a simple wishbone slave	Interna	Pasando Jugo
Bus Select Lines	Interna	Pasando Jugo
FFT debugging	Interna	Pasando Jugo
Debugging an FPGA through the serial port--first steps	Interna	Pasando Jugo
That first serial port: Debugging when you are blind	Interna	Pasando Jugo
Building a simple bus	Interna	Pasando Jugo
Moving to memory	Interna	Pasando Jugo
A Vision for Controlling FPGA Logic	Interna	Pasando Jugo
Which comes first: the CPU or the peripherals?	Interna	Pasando Jugo
Knight Rider	Interna	Pasando Jugo
FPGA Hell	Interna	Pasando Jugo
Blinky	Interna	Pasando Jugo
Most common Digilent FPGA support requests	Interna	Pasando Jugo
Cannot be done	Interna	Pasando Jugo
Welcome to the ZipCPU blog!	Interna	Pasando Jugo
via RSS	Interna	Pasando Jugo

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